From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erUKy-0004Ad-30 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 14:57:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erUKv-0001Zs-1S for qemu-devel@nongnu.org; Thu, 01 Mar 2018 14:57:56 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:59066 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erUKu-0001ZQ-RW for qemu-devel@nongnu.org; Thu, 01 Mar 2018 14:57:52 -0500 Date: Thu, 1 Mar 2018 20:57:16 +0100 From: Radim =?utf-8?B?S3LEjW3DocWZ?= Message-ID: <20180301195715.GA28948@flask> References: <1519439425-27883-1-git-send-email-babu.moger@amd.com> <1519439425-27883-4-git-send-email-babu.moger@amd.com> <20180228182420.GC8418@flask> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 3/5] target/i386: Add support for CPUID_8000_001E for AMD List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Moger, Babu" Cc: "pbonzini@redhat.com" , "rth@twiddle.net" , "ehabkost@redhat.com" , "mtosatti@redhat.com" , "qemu-devel@nongnu.org" , "kvm@vger.kernel.org" , "pixo@polepetko.eu" , "Hook, Gary" 2018-02-28 22:18+0000, Moger, Babu: > > -----Original Message----- > > From: Radim Kr=C4=8Dm=C3=A1=C5=99 [mailto:rkrcmar@redhat.com] > > Sent: Wednesday, February 28, 2018 12:24 PM > > To: Moger, Babu > > Cc: pbonzini@redhat.com; rth@twiddle.net; ehabkost@redhat.com; > > mtosatti@redhat.com; qemu-devel@nongnu.org; kvm@vger.kernel.org; > > pixo@polepetko.eu; Hook, Gary > > Subject: Re: [PATCH v2 3/5] target/i386: Add support for CPUID_8000_0= 01E > > for AMD > >=20 > > 2018-02-23 21:30-0500, Babu Moger: > > > From: Stanislav Lanci > > > > > > Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT > > > feature is supported. This is required to support hyperthreading > > > feature on AMD CPUS. These are supported via CPUID_8000_001E > > extended > > > functions. > > > > > > Signed-off-by: Stanislav Lanci > > > Signed-off-by: Babu Moger > > > --- > > > target/i386/cpu.c | 8 ++++++++ > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > > index a5a480e..191e850 100644 > > > --- a/target/i386/cpu.c > > > +++ b/target/i386/cpu.c > > > @@ -3666,6 +3666,14 @@ void cpu_x86_cpuid(CPUX86State *env, > > uint32_t index, uint32_t count, > > > *edx =3D 0; > > > } > > > break; > > > + case 0x8000001E: > > > + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT= ) { > > > + *eax =3D cpu->apic_id; > > > + *ebx =3D (cs->nr_threads - 1) << 8 | cpu->core_id; > >=20 > > Do we somewhere assert that AMD cannot have cpu->core_id > 255? > > (qemu does allow weird configurations.) >=20 > I don't see specific assert on core_id. But, I see that qemu does not= allow nr_cores more than 255. > Also I see that core_id is iterated based on nr_cores. If you strongly= believe we need to add assert here, I will add it.=20 > Let me know. A user can emulate AMD with x2apic and intel-iommu to allow more than 255 vcpus and all of them can be a separate core (or its own socket), which would overflow this (or the next counter). Forbidding that crazy configuration may be preferable, but an assert won't hurt now, thanks. > > Thanks. > >=20 > > > + *ecx =3D cpu->socket_id; > > > + *edx =3D 0; > > > + } > > > + break; > > > case 0xC0000000: > > > *eax =3D env->cpuid_xlevel2; > > > *ebx =3D 0; > > > -- > > > 1.8.3.1 > > >