From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erpr5-0002DN-Mt for qemu-devel@nongnu.org; Fri, 02 Mar 2018 13:56:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erpr5-0003Zs-0Y for qemu-devel@nongnu.org; Fri, 02 Mar 2018 13:56:31 -0500 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:46694) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1erpr4-0003Z5-R6 for qemu-devel@nongnu.org; Fri, 02 Mar 2018 13:56:30 -0500 Received: by mail-pl0-x241.google.com with SMTP id y8-v6so6186057pll.13 for ; Fri, 02 Mar 2018 10:56:30 -0800 (PST) From: Richard Henderson Date: Fri, 2 Mar 2018 10:56:21 -0800 Message-Id: <20180302185622.27780-3-richard.henderson@linaro.org> In-Reply-To: <20180302185622.27780-1-richard.henderson@linaro.org> References: <20180302185622.27780-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PULL 2/3] tcg/i386: Support INDEX_op_dup2_vec for -m32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Unknown why -m32 was passing with gcc but not clang; it should have failed for both. This would be used for tcg_gen_dup_i64_vec, and visible with the right TB and an aarch64 guest. Reported-by: Max Reitz Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fc05909d1d..d7e59e79c5 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2696,6 +2696,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_x86_packus_vec: insn = packus_insn[vece]; goto gen_simd; +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: + /* Constraints have already placed both 32-bit inputs in xmm regs. */ + insn = OPC_PUNPCKLDQ; + goto gen_simd; +#endif gen_simd: tcg_debug_assert(insn != OPC_UD2); if (type == TCG_TYPE_V256) { @@ -3045,6 +3051,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_x86_vperm2i128_vec: case INDEX_op_x86_punpckl_vec: case INDEX_op_x86_punpckh_vec: +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: +#endif return &x_x_x; case INDEX_op_dup_vec: case INDEX_op_shli_vec: -- 2.14.3