* [Qemu-devel] [PATCH v2 01/30] util/cutils: extract byte-based definitions into a new header: "qemu/cunits.h"
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [RFC PATCH v2 02/30] hw: include "qemu/cunits.h" and clean unused "qemu/cutils.h" Philippe Mathieu-Daudé
` (28 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel
(added in 076b35b5a56)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
include/qemu/cunits.h | 11 +++++++++++
include/qemu/cutils.h | 8 +-------
2 files changed, 12 insertions(+), 7 deletions(-)
create mode 100644 include/qemu/cunits.h
diff --git a/include/qemu/cunits.h b/include/qemu/cunits.h
new file mode 100644
index 0000000000..c0207b7611
--- /dev/null
+++ b/include/qemu/cunits.h
@@ -0,0 +1,11 @@
+#ifndef QEMU_CUNITS_H
+#define QEMU_CUNITS_H
+
+#define K_BYTE (1ULL << 10)
+#define M_BYTE (1ULL << 20)
+#define G_BYTE (1ULL << 30)
+#define T_BYTE (1ULL << 40)
+#define P_BYTE (1ULL << 50)
+#define E_BYTE (1ULL << 60)
+
+#endif
diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h
index f0878eaafa..01184a70b3 100644
--- a/include/qemu/cutils.h
+++ b/include/qemu/cutils.h
@@ -2,6 +2,7 @@
#define QEMU_CUTILS_H
#include "qemu/fprintf-fn.h"
+#include "qemu/cunits.h"
/**
* pstrcpy:
@@ -143,13 +144,6 @@ int qemu_strtosz(const char *nptr, char **end, uint64_t *result);
int qemu_strtosz_MiB(const char *nptr, char **end, uint64_t *result);
int qemu_strtosz_metric(const char *nptr, char **end, uint64_t *result);
-#define K_BYTE (1ULL << 10)
-#define M_BYTE (1ULL << 20)
-#define G_BYTE (1ULL << 30)
-#define T_BYTE (1ULL << 40)
-#define P_BYTE (1ULL << 50)
-#define E_BYTE (1ULL << 60)
-
/* used to print char* safely */
#define STR_OR_NULL(str) ((str) ? (str) : "null")
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [RFC PATCH v2 02/30] hw: include "qemu/cunits.h" and clean unused "qemu/cutils.h"
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 01/30] util/cutils: extract byte-based definitions into a new header: "qemu/cunits.h" Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 18:57 ` Daniel P. Berrangé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 03/30] hw/block/nvme: include the "qemu/cutils.h" in the source file Philippe Mathieu-Daudé
` (27 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Subbaraya Sundeep,
Peter Maydell, Paul Burton, Eduardo Habkost, Marcel Apfelbaum,
Edgar E. Iglesias, Richard Henderson, Michael Walle,
Aurelien Jarno, Yongbok Kim, Chris Wulff, Marek Vasut,
Alexander Graf, David Gibson, Hervé Poussineau,
Mark Cave-Ayland, Artyom Tarasenko, Gerd Hoffmann,
Samuel Thibault, open list:ARM, open list:New World
These files were including "qemu/cutils.h" to use the byte-based size
definitions, now available in "qemu/cunits.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Thomas suggested:
Instead of adding this to a header and creating yet another possible
recompile-the-world dependency this way, wouldn't it be better to
include the cunits.h only from the .c files that need the definitions?
include/hw/hw.h | 1 +
hw/arm/msf2-soc.c | 1 -
hw/arm/msf2-som.c | 1 -
hw/core/loader-fit.c | 1 -
hw/core/loader.c | 1 -
hw/core/machine.c | 1 -
hw/cris/boot.c | 1 -
hw/display/sm501.c | 1 -
hw/hppa/machine.c | 1 -
hw/lm32/milkymist.c | 1 -
hw/microblaze/boot.c | 1 -
hw/mips/boston.c | 1 -
hw/misc/mos6522.c | 1 -
hw/nios2/boot.c | 1 -
hw/ppc/mac_newworld.c | 1 -
hw/ppc/mac_oldworld.c | 1 -
hw/ppc/pnv.c | 1 -
hw/ppc/prep.c | 1 -
hw/ppc/spapr_rtas.c | 1 -
hw/sd/sdhci.c | 1 -
hw/sparc/sun4m.c | 1 -
hw/sparc64/sun4u.c | 1 -
hw/usb/dev-serial.c | 1 -
hw/usb/dev-storage.c | 1 -
24 files changed, 1 insertion(+), 23 deletions(-)
diff --git a/include/hw/hw.h b/include/hw/hw.h
index ab4950c312..8249448cac 100644
--- a/include/hw/hw.h
+++ b/include/hw/hw.h
@@ -14,6 +14,7 @@
#include "migration/qemu-file-types.h"
#include "qemu/module.h"
#include "sysemu/reset.h"
+#include "qemu/cunits.h"
void QEMU_NORETURN hw_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index a8ec2cdf36..952cda45ed 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -30,7 +30,6 @@
#include "hw/char/serial.h"
#include "hw/boards.h"
#include "sysemu/block-backend.h"
-#include "qemu/cutils.h"
#include "hw/arm/msf2-soc.h"
#include "hw/misc/unimp.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 0795a3a3a1..d3e6ed00fe 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -28,7 +28,6 @@
#include "hw/boards.h"
#include "hw/arm/arm.h"
#include "exec/address-spaces.h"
-#include "qemu/cutils.h"
#include "hw/arm/msf2-soc.h"
#include "cpu.h"
diff --git a/hw/core/loader-fit.c b/hw/core/loader-fit.c
index 0c4a7207f4..0208e5b357 100644
--- a/hw/core/loader-fit.c
+++ b/hw/core/loader-fit.c
@@ -22,7 +22,6 @@
#include "exec/memory.h"
#include "hw/loader.h"
#include "hw/loader-fit.h"
-#include "qemu/cutils.h"
#include "qemu/error-report.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 76b244c508..ce0aefe5c2 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -54,7 +54,6 @@
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
-#include "qemu/cutils.h"
#include <zlib.h>
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 5d445839e8..7a7ec0c1e1 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -19,7 +19,6 @@
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "qemu/error-report.h"
-#include "qemu/cutils.h"
#include "sysemu/qtest.h"
static char *machine_get_accel(Object *obj, Error **errp)
diff --git a/hw/cris/boot.c b/hw/cris/boot.c
index f896ed7f86..7d423ed92f 100644
--- a/hw/cris/boot.c
+++ b/hw/cris/boot.c
@@ -29,7 +29,6 @@
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"
-#include "qemu/cutils.h"
static void main_cpu_reset(void *opaque)
{
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index f4bb33c279..00cf8358e2 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -24,7 +24,6 @@
*/
#include "qemu/osdep.h"
-#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 19033e268d..22a15112df 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -17,7 +17,6 @@
#include "hw/timer/i8254.h"
#include "hw/char/serial.h"
#include "hw/hppa/hppa_sys.h"
-#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu/log.h"
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index 85d64fe58d..471a74eaa1 100644
--- a/hw/lm32/milkymist.c
+++ b/hw/lm32/milkymist.c
@@ -34,7 +34,6 @@
#include "milkymist-hw.h"
#include "lm32.h"
#include "exec/address-spaces.h"
-#include "qemu/cutils.h"
#define BIOS_FILENAME "mmone-bios.bin"
#define BIOS_OFFSET 0x00860000
diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
index 35bfeda7aa..5b30d63c17 100644
--- a/hw/microblaze/boot.c
+++ b/hw/microblaze/boot.c
@@ -34,7 +34,6 @@
#include "sysemu/sysemu.h"
#include "hw/loader.h"
#include "elf.h"
-#include "qemu/cutils.h"
#include "boot.h"
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index fb23161b33..e99f3638cf 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -32,7 +32,6 @@
#include "hw/mips/cpudevs.h"
#include "hw/pci-host/xilinx-pcie.h"
#include "qapi/error.h"
-#include "qemu/cutils.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "chardev/char.h"
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 8ad9fc831e..b55e6acbe2 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -29,7 +29,6 @@
#include "hw/misc/mos6522.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
-#include "qemu/cutils.h"
#include "qemu/log.h"
#include "trace.h"
diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c
index 94f436e7fb..771e00267b 100644
--- a/hw/nios2/boot.c
+++ b/hw/nios2/boot.c
@@ -38,7 +38,6 @@
#include "sysemu/sysemu.h"
#include "hw/loader.h"
#include "elf.h"
-#include "qemu/cutils.h"
#include "boot.h"
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 4e1298ee50..77d4e9b013 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -71,7 +71,6 @@
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h"
-#include "qemu/cutils.h"
#include "trace.h"
#define MAX_IDE_BUS 2
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index d0d21d2392..c245251c5c 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -45,7 +45,6 @@
#include "kvm_ppc.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
-#include "qemu/cutils.h"
#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 98ee3c607a..3d943dd71b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -31,7 +31,6 @@
#include "hw/ppc/pnv_core.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"
-#include "qemu/cutils.h"
#include "qapi/visitor.h"
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 096d4d4cfb..f7c0a48558 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -50,7 +50,6 @@
#include "exec/address-spaces.h"
#include "trace.h"
#include "elf.h"
-#include "qemu/cutils.h"
#include "kvm_ppc.h"
/* SMP is not enabled, for now */
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 4bb939d3d1..7e26a9fb5a 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -43,7 +43,6 @@
#include <libfdt.h>
#include "hw/ppc/spapr_drc.h"
-#include "qemu/cutils.h"
#include "trace.h"
#include "hw/ppc/fdt.h"
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 97b4a473c8..cf935c2008 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -34,7 +34,6 @@
#include "hw/sd/sdhci.h"
#include "sdhci-internal.h"
#include "qemu/log.h"
-#include "qemu/cutils.h"
#include "trace.h"
#define TYPE_SDHCI_BUS "sdhci-bus"
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 61eb424bbc..9d82490794 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -46,7 +46,6 @@
#include "elf.h"
#include "sysemu/block-backend.h"
#include "trace.h"
-#include "qemu/cutils.h"
/*
* Sun4m architecture was used in the following machines:
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index da28ab9413..b84589e0b6 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -50,7 +50,6 @@
#include "hw/loader.h"
#include "elf.h"
#include "trace.h"
-#include "qemu/cutils.h"
#define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000
diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c
index 2829dda391..5e610722ee 100644
--- a/hw/usb/dev-serial.c
+++ b/hw/usb/dev-serial.c
@@ -11,7 +11,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
-#include "qemu/cutils.h"
#include "qemu/error-report.h"
#include "hw/usb.h"
#include "hw/usb/desc.h"
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index b56c75a73a..d02c5d76c6 100644
--- a/hw/usb/dev-storage.c
+++ b/hw/usb/dev-storage.c
@@ -22,7 +22,6 @@
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "qapi/visitor.h"
-#include "qemu/cutils.h"
//#define DEBUG_MSD
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [RFC PATCH v2 02/30] hw: include "qemu/cunits.h" and clean unused "qemu/cutils.h"
2018-03-05 11:27 ` [Qemu-devel] [RFC PATCH v2 02/30] hw: include "qemu/cunits.h" and clean unused "qemu/cutils.h" Philippe Mathieu-Daudé
@ 2018-03-05 18:57 ` Daniel P. Berrangé
2018-03-05 19:01 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
0 siblings, 1 reply; 40+ messages in thread
From: Daniel P. Berrangé @ 2018-03-05 18:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-trivial, Peter Maydell, Michael Walle, Mark Cave-Ayland,
qemu-devel, Gerd Hoffmann, Edgar E. Iglesias, Yongbok Kim,
Marek Vasut, Alexander Graf, Hervé Poussineau,
Marcel Apfelbaum, Samuel Thibault, Richard Henderson,
Artyom Tarasenko, Eduardo Habkost, open list:ARM, David Gibson,
Chris Wulff, Subbaraya Sundeep, Paul Burton, open list:New World,
Aurelien Jarno
On Mon, Mar 05, 2018 at 08:27:04AM -0300, Philippe Mathieu-Daudé wrote:
> These files were including "qemu/cutils.h" to use the byte-based size
> definitions, now available in "qemu/cunits.h".
I know I'm "complaining" about bike-shed colour here....
Feels like just calling it units.h is sufficient - all our .h code is
C code so don't need reminding of it by filename, particularly since
we're avoiding system header clash by using the qemu/ prefix on #includes.
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Regardless of whether you rename it or not though,
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [RFC PATCH v2 02/30] hw: include "qemu/cunits.h" and clean unused "qemu/cutils.h"
2018-03-05 18:57 ` Daniel P. Berrangé
@ 2018-03-05 19:01 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 19:01 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: Peter Maydell, Mark Cave-Ayland, qemu-devel, Michael Walle,
Yongbok Kim, Marek Vasut, qemu-trivial, Alexander Graf,
Hervé Poussineau, Marcel Apfelbaum, Samuel Thibault,
Richard Henderson, Artyom Tarasenko, Eduardo Habkost,
open list:ARM, David Gibson, Chris Wulff, Subbaraya Sundeep,
Paul Burton, open list:New World, Aurelien Jarno, Gerd Hoffmann
On 03/05/2018 03:57 PM, Daniel P. Berrangé wrote:
> On Mon, Mar 05, 2018 at 08:27:04AM -0300, Philippe Mathieu-Daudé wrote:
>> These files were including "qemu/cutils.h" to use the byte-based size
>> definitions, now available in "qemu/cunits.h".
>
> I know I'm "complaining" about bike-shed colour here....
>
> Feels like just calling it units.h is sufficient - all our .h code is
> C code so don't need reminding of it by filename, particularly since
> we're avoiding system header clash by using the qemu/ prefix on #includes.
I like your suggestion :)
>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Regardless of whether you rename it or not though,
>
> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Thanks!
>
>
> Regards,
> Daniel
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v2 03/30] hw/block/nvme: include the "qemu/cutils.h" in the source file
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 01/30] util/cutils: extract byte-based definitions into a new header: "qemu/cunits.h" Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [RFC PATCH v2 02/30] hw: include "qemu/cunits.h" and clean unused "qemu/cutils.h" Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 04/30] hw/lm32/milkymist: remove unused include Philippe Mathieu-Daudé
` (26 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Keith Busch, Kevin Wolf,
Max Reitz, open list:nvme
where it is used.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
hw/block/nvme.h | 1 -
hw/block/nvme.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 8f3981121d..cabcf20c32 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -1,6 +1,5 @@
#ifndef HW_NVME_H
#define HW_NVME_H
-#include "qemu/cutils.h"
#include "block/nvme.h"
typedef struct NvmeAsyncEvent {
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 85d2406400..811084b6a7 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -35,6 +35,7 @@
#include "sysemu/block-backend.h"
#include "qemu/log.h"
+#include "qemu/cutils.h"
#include "trace.h"
#include "nvme.h"
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 04/30] hw/lm32/milkymist: remove unused include
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 03/30] hw/block/nvme: include the "qemu/cutils.h" in the source file Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 05/30] hw/mips/r4k: constify params_size Philippe Mathieu-Daudé
` (25 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Michael Walle
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Thomas Huth <thuth@redhat.com>
---
hw/lm32/milkymist.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index 471a74eaa1..c28379399f 100644
--- a/hw/lm32/milkymist.c
+++ b/hw/lm32/milkymist.c
@@ -30,7 +30,6 @@
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
-#include "sysemu/block-backend.h"
#include "milkymist-hw.h"
#include "lm32.h"
#include "exec/address-spaces.h"
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 05/30] hw/mips/r4k: constify params_size
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 04/30] hw/lm32/milkymist: remove unused include Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 06/30] hw/mips: use the BYTE-based definitions Philippe Mathieu-Daudé
` (24 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Aurelien Jarno,
Yongbok Kim
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/mips_r4k.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index 830ee7732c..2556786def 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -79,8 +79,9 @@ typedef struct ResetData {
static int64_t load_kernel(void)
{
+ const size_t params_size = 264;
int64_t entry, kernel_high;
- long kernel_size, initrd_size, params_size;
+ long kernel_size, initrd_size;
ram_addr_t initrd_offset;
uint32_t *params_buf;
int big_endian;
@@ -128,7 +129,6 @@ static int64_t load_kernel(void)
}
/* Store command line. */
- params_size = 264;
params_buf = g_malloc(params_size);
params_buf[0] = tswap32(ram_size);
@@ -143,7 +143,7 @@ static int64_t load_kernel(void)
}
rom_add_blob_fixed("params", params_buf, params_size,
- (16 << 20) - 264);
+ (16 << 20) - params_size);
g_free(params_buf);
return entry;
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 06/30] hw/mips: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 05/30] hw/mips/r4k: constify params_size Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 07/30] hw/arm: " Philippe Mathieu-Daudé
` (23 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Paul Burton,
Aurelien Jarno, Yongbok Kim
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/intc/mips_gic.h | 2 +-
include/hw/mips/bios.h | 2 +-
hw/mips/boston.c | 2 +-
hw/mips/mips_fulong2e.c | 6 +++---
hw/mips/mips_malta.c | 19 ++++++++++---------
hw/mips/mips_r4k.c | 10 +++++-----
hw/misc/mips_itu.c | 2 +-
hw/pci-host/xilinx-pcie.c | 4 ++--
8 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/include/hw/intc/mips_gic.h b/include/hw/intc/mips_gic.h
index b98d50094a..5ae5a74249 100644
--- a/include/hw/intc/mips_gic.h
+++ b/include/hw/intc/mips_gic.h
@@ -19,7 +19,7 @@
/* The MIPS default location */
#define GIC_BASE_ADDR 0x1bdc0000ULL
-#define GIC_ADDRSPACE_SZ (128 * 1024)
+#define GIC_ADDRSPACE_SZ (128 * K_BYTE)
/* Constants */
#define GIC_POL_POS 1
diff --git a/include/hw/mips/bios.h b/include/hw/mips/bios.h
index b4b88ac43d..c70fab193a 100644
--- a/include/hw/mips/bios.h
+++ b/include/hw/mips/bios.h
@@ -1,6 +1,6 @@
#include "cpu.h"
-#define BIOS_SIZE (4 * 1024 * 1024)
+#define BIOS_SIZE (4 * M_BYTE)
#ifdef TARGET_WORDS_BIGENDIAN
#define BIOS_FILENAME "mips_bios.bin"
#else
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index e99f3638cf..1a1be57ba0 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -436,7 +436,7 @@ static void boston_mach_init(MachineState *machine)
bool is_64b;
if ((machine->ram_size % G_BYTE) ||
- (machine->ram_size > (2 * G_BYTE))) {
+ (machine->ram_size > 2 * G_BYTE)) {
error_report("Memory size must be 1GB or 2GB");
exit(1);
}
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index f68c625666..428bf11fb4 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -164,7 +164,7 @@ static int64_t load_kernel (CPUMIPSState *env)
/* Setup minimum environment variables */
prom_set(prom_buf, index++, "busclock=33000000");
prom_set(prom_buf, index++, "cpuclock=100000000");
- prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024);
+ prom_set(prom_buf, index++, "memsize=%llu", loaderparams.ram_size / M_BYTE);
prom_set(prom_buf, index++, "modetty0=38400n8r");
prom_set(prom_buf, index++, NULL);
@@ -281,10 +281,10 @@ static void mips_fulong2e_init(MachineState *machine)
qemu_register_reset(main_cpu_reset, cpu);
/* fulong 2e has 256M ram. */
- ram_size = 256 * 1024 * 1024;
+ ram_size = 256 * M_BYTE;
/* fulong 2e has a 1M flash.Winbond W39L040AP70Z */
- bios_size = 1024 * 1024;
+ bios_size = 1 * M_BYTE;
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 6f0deb99e7..7d27502b1a 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1033,9 +1033,9 @@ void mips_malta_init(MachineState *machine)
mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
/* allocate RAM */
- if (ram_size > (2048u << 20)) {
- error_report("Too much memory for this machine: %dMB, maximum 2048MB",
- ((unsigned int)ram_size / (1 << 20)));
+ if (ram_size > 2 * G_BYTE) {
+ error_report("Too much memory for this machine: %lluMB, maximum 2048MB",
+ ram_size / M_BYTE);
exit(1);
}
@@ -1046,17 +1046,18 @@ void mips_malta_init(MachineState *machine)
/* alias for pre IO hole access */
memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
- ram_high, 0, MIN(ram_size, (256 << 20)));
+ ram_high, 0, MIN(ram_size, 256 * M_BYTE));
memory_region_add_subregion(system_memory, 0, ram_low_preio);
/* alias for post IO hole access, if there is enough RAM */
- if (ram_size > (512 << 20)) {
+ if (ram_size > 512 * M_BYTE) {
ram_low_postio = g_new(MemoryRegion, 1);
memory_region_init_alias(ram_low_postio, NULL,
"mips_malta_low_postio.ram",
- ram_high, 512 << 20,
- ram_size - (512 << 20));
- memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio);
+ ram_high, 512 * M_BYTE,
+ ram_size - 512 * M_BYTE);
+ memory_region_add_subregion(system_memory, 512 * M_BYTE,
+ ram_low_postio);
}
/* generate SPD EEPROM data */
@@ -1090,7 +1091,7 @@ void mips_malta_init(MachineState *machine)
bios = pflash_cfi01_get_memory(fl);
fl_idx++;
if (kernel_filename) {
- ram_low_size = MIN(ram_size, 256 << 20);
+ ram_low_size = MIN(ram_size, 256 * M_BYTE);
/* For KVM we reserve 1MB of RAM for running bootloader */
if (kvm_enabled()) {
ram_low_size -= 0x100000;
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index 2556786def..b35f1649af 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -143,7 +143,7 @@ static int64_t load_kernel(void)
}
rom_add_blob_fixed("params", params_buf, params_size,
- (16 << 20) - params_size);
+ 16 * M_BYTE - params_size);
g_free(params_buf);
return entry;
@@ -158,7 +158,7 @@ static void main_cpu_reset(void *opaque)
env->active_tc.PC = s->vector;
}
-static const int sector_len = 32 * 1024;
+static const int sector_len = 32 * K_BYTE;
static
void mips_r4k_init(MachineState *machine)
{
@@ -194,9 +194,9 @@ void mips_r4k_init(MachineState *machine)
qemu_register_reset(main_cpu_reset, reset_info);
/* allocate RAM */
- if (ram_size > (256 << 20)) {
- error_report("Too much memory for this machine: %dMB, maximum 256MB",
- ((unsigned int)ram_size / (1 << 20)));
+ if (ram_size > 256 * M_BYTE) {
+ error_report("Too much memory for this machine: %lluMB, maximum 256MB",
+ ram_size / M_BYTE);
exit(1);
}
memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size);
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index ef935b51a8..fc72d376e4 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -83,7 +83,7 @@ static void itc_reconfigure(MIPSITUState *tag)
uint64_t *am = &tag->ITCAddressMap[0];
MemoryRegion *mr = &tag->storage_io;
hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
- uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
+ uint64_t size = (1 * K_BYTE) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
memory_region_transaction_begin();
diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c
index 044e312dc1..b7272d173a 100644
--- a/hw/pci-host/xilinx-pcie.c
+++ b/hw/pci-host/xilinx-pcie.c
@@ -158,9 +158,9 @@ static void xilinx_pcie_host_init(Object *obj)
static Property xilinx_pcie_host_props[] = {
DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
- DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20),
+ DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * M_BYTE),
DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
- DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20),
+ DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * M_BYTE),
DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
DEFINE_PROP_END_OF_LIST(),
};
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 07/30] hw/arm: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 06/30] hw/mips: use the BYTE-based definitions Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-06 15:46 ` Alex Bennée
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 08/30] hw/i386: " Philippe Mathieu-Daudé
` (22 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Peter Maydell,
Antony Pavlov, Andrzej Zaborowski, Jan Kiszka, Edgar E. Iglesias,
Alistair Francis, Peter Chubb, Peter Crosthwaite, open list:ARM
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
include/hw/arm/stm32f205_soc.h | 4 ++--
hw/arm/boot.c | 6 +++---
hw/arm/collie.c | 4 ++--
hw/arm/digic_boards.c | 6 +++---
hw/arm/gumstix.c | 2 +-
hw/arm/integratorcp.c | 2 +-
hw/arm/mainstone.c | 2 +-
hw/arm/musicpal.c | 8 ++++----
hw/arm/omap_sx1.c | 8 ++++----
hw/arm/raspi.c | 4 ++--
hw/arm/stellaris.c | 4 ++--
hw/arm/versatilepb.c | 4 ++--
hw/arm/vexpress.c | 6 +++---
hw/arm/virt.c | 4 ++--
hw/arm/xilinx_zynq.c | 4 ++--
hw/misc/aspeed_sdmc.c | 8 ++++----
hw/misc/imx7_gpr.c | 2 +-
hw/misc/omap_gpmc.c | 4 ++--
hw/ssi/aspeed_smc.c | 28 ++++++++++++++--------------
19 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 922a733f88..e30ae33c65 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -43,9 +43,9 @@
#define STM_NUM_SPIS 3
#define FLASH_BASE_ADDRESS 0x08000000
-#define FLASH_SIZE (1024 * 1024)
+#define FLASH_SIZE (1 * M_BYTE)
#define SRAM_BASE_ADDRESS 0x20000000
-#define SRAM_SIZE (128 * 1024)
+#define SRAM_SIZE (128 * K_BYTE)
typedef struct STM32F205State {
/*< private >*/
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 6d0c92ab88..51df96a6c8 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -1015,7 +1015,7 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
* the initrd at 128MB.
*/
info->initrd_start = info->loader_start +
- MIN(info->ram_size / 2, 128 * 1024 * 1024);
+ MIN(info->ram_size / 2, 128 * M_BYTE);
/* Assume that raw images are linux kernels, and ELF images are not. */
kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,
@@ -1102,13 +1102,13 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
*
* Let's play safe and prealign it to 2MB to give us some space.
*/
- align = 2 * 1024 * 1024;
+ align = 2 * M_BYTE;
} else {
/*
* Some 32bit kernels will trash anything in the 4K page the
* initrd ends in, so make sure the DTB isn't caught up in that.
*/
- align = 4096;
+ align = 4 * K_BYTE;
}
/* Place the DTB after the initrd in memory with alignment. */
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index f8c566e2e5..1695863629 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -39,12 +39,12 @@ static void collie_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- (64 * 1024), 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
+ 64 * K_BYTE, 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
dinfo = drive_get(IF_PFLASH, 0, 1);
pflash_cfi01_register(SA_CS1, NULL, "collie.fl2", 0x02000000,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- (64 * 1024), 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
+ 64 * K_BYTE, 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
sysbus_create_simple("scoop", 0x40800000, NULL);
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 9f11dcd11f..04e52e776f 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -126,8 +126,8 @@ static void digic_load_rom(DigicBoardState *s, hwaddr addr,
static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
const char *def_filename)
{
-#define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024)
-#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024)
+#define FLASH_K8P3215UQB_SIZE (4 * M_BYTE)
+#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * K_BYTE)
pflash_cfi02_register(addr, NULL, "pflash", FLASH_K8P3215UQB_SIZE,
NULL, FLASH_K8P3215UQB_SECTOR_SIZE,
@@ -141,7 +141,7 @@ static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
}
static DigicBoard digic4_board_canon_a1100 = {
- .ram_size = 64 * 1024 * 1024,
+ .ram_size = 64 * M_BYTE,
.add_rom1 = digic4_add_k8p3215uqb_rom,
.rom1_def_filename = "canon-a1100-rom1.bin",
};
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index ea2a3c532d..fc15df1d12 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -47,7 +47,7 @@
#include "sysemu/qtest.h"
#include "cpu.h"
-static const int sector_len = 128 * 1024;
+static const int sector_len = 128 * K_BYTE;
static void connex_init(MachineState *machine)
{
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index e8303b83be..4e711194ef 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -609,7 +609,7 @@ static void integratorcp_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
- qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
+ qdev_prop_set_uint32(dev, "memsz", ram_size / M_BYTE);
qdev_init_nofail(dev);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 4215c025fc..37c21ed6d0 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -115,7 +115,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
MachineState *machine,
enum mainstone_model_e model, int arm_id)
{
- uint32_t sector_len = 256 * 1024;
+ uint32_t sector_len = 256 * K_BYTE;
hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *mpu;
DeviceState *mst_irq;
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 38d7322a19..d6d1ce75c5 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -62,8 +62,8 @@
#define MP_SRAM_BASE 0xC0000000
#define MP_SRAM_SIZE 0x00020000
-#define MP_RAM_DEFAULT_SIZE 32*1024*1024
-#define MP_FLASH_SIZE_MAX 32*1024*1024
+#define MP_RAM_DEFAULT_SIZE (32 * M_BYTE)
+#define MP_FLASH_SIZE_MAX (32 * M_BYTE)
#define MP_TIMER1_IRQ 4
#define MP_TIMER2_IRQ 5
@@ -1625,8 +1625,8 @@ static void musicpal_init(MachineState *machine)
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
flash_size = blk_getlength(blk);
- if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
- flash_size != 32*1024*1024) {
+ if (flash_size != 8 * M_BYTE && flash_size != 16 * M_BYTE &&
+ flash_size != 32 * M_BYTE) {
error_report("Invalid flash image size");
exit(1);
}
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index eccc19c77b..729af8bb80 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -88,10 +88,10 @@ static const MemoryRegionOps static_ops = {
};
#define sdram_size 0x02000000
-#define sector_size (128 * 1024)
-#define flash0_size (16 * 1024 * 1024)
-#define flash1_size ( 8 * 1024 * 1024)
-#define flash2_size (32 * 1024 * 1024)
+#define sector_size (128 * K_BYTE)
+#define flash0_size (16 * M_BYTE)
+#define flash1_size (8 * M_BYTE)
+#define flash2_size (32 * M_BYTE)
#define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
#define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index a37881433c..4b54fa5ad4 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -183,7 +183,7 @@ static void raspi2_machine_init(MachineClass *mc)
mc->max_cpus = BCM2836_NCPUS;
mc->min_cpus = BCM2836_NCPUS;
mc->default_cpus = BCM2836_NCPUS;
- mc->default_ram_size = 1024 * 1024 * 1024;
+ mc->default_ram_size = 1 * G_BYTE;
mc->ignore_memory_transaction_failures = true;
};
DEFINE_MACHINE("raspi2", raspi2_machine_init)
@@ -206,7 +206,7 @@ static void raspi3_machine_init(MachineClass *mc)
mc->max_cpus = BCM2836_NCPUS;
mc->min_cpus = BCM2836_NCPUS;
mc->default_cpus = BCM2836_NCPUS;
- mc->default_ram_size = 1024 * 1024 * 1024;
+ mc->default_ram_size = 1 * G_BYTE;
}
DEFINE_MACHINE("raspi3", raspi3_machine_init)
#endif
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index de7c0fc4a6..8ff7567126 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1284,8 +1284,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *system_memory = get_system_memory();
- flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
- sram_size = ((board->dc0 >> 18) + 1) * 1024;
+ flash_size = (((board->dc0 & 0xffff) + 1) << 1) * K_BYTE;
+ sram_size = ((board->dc0 >> 18) + 1) * K_BYTE;
/* Flash programming is done via the SCU, so pretend it is ROM. */
memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 418792cd02..041f12beb7 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -26,8 +26,8 @@
#include "hw/char/pl011.h"
#define VERSATILE_FLASH_ADDR 0x34000000
-#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
-#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
+#define VERSATILE_FLASH_SIZE (64 * M_BYTE)
+#define VERSATILE_FLASH_SECT_SIZE (256 * K_BYTE)
/* Primary interrupt controller. */
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 9fad79177a..7b12dfca41 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -45,8 +45,8 @@
#include "hw/cpu/a15mpcore.h"
#define VEXPRESS_BOARD_ID 0x8e0
-#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
-#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
+#define VEXPRESS_FLASH_SIZE (64 * M_BYTE)
+#define VEXPRESS_FLASH_SECT_SIZE (256 * K_BYTE)
/* Number of virtio transports to create (0..8; limited by
* number of available IRQ lines).
@@ -355,7 +355,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
* warning if we are on a host where ram_addr_t is 32 bits.
*/
uint64_t rsz = ram_size;
- if (rsz > (30ULL * 1024 * 1024 * 1024)) {
+ if (rsz > 30 * G_BYTE) {
error_report("vexpress-a15: cannot model more than 30GB RAM");
exit(1);
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index dbb3c8036a..8202a428e0 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -110,7 +110,7 @@ static ARMPlatformBusSystemParams platform_bus_params;
* terabyte of physical address space.)
*/
#define RAMLIMIT_GB 255
-#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
+#define RAMLIMIT_BYTES (RAMLIMIT_GB * G_BYTE)
/* Addresses and sizes of our components.
* 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
@@ -783,7 +783,7 @@ static void create_one_flash(const char *name, hwaddr flashbase,
DriveInfo *dinfo = drive_get_next(IF_PFLASH);
DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- const uint64_t sectorlength = 256 * 1024;
+ const uint64_t sectorlength = 256 * K_BYTE;
if (dinfo) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 0f76333770..7a68503e68 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -40,8 +40,8 @@
#define NUM_QSPI_FLASHES 2
#define NUM_QSPI_BUSSES 2
-#define FLASH_SIZE (64 * 1024 * 1024)
-#define FLASH_SECTOR_SIZE (128 * 1024)
+#define FLASH_SIZE (64 * M_BYTE)
+#define FLASH_SECTOR_SIZE (128 * K_BYTE)
#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 0df008e52a..eaf090b7b1 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -149,7 +149,7 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
static int ast2400_rambits(AspeedSDMCState *s)
{
- switch (s->ram_size >> 20) {
+ switch (s->ram_size / M_BYTE) {
case 64:
return ASPEED_SDMC_DRAM_64MB;
case 128:
@@ -165,13 +165,13 @@ static int ast2400_rambits(AspeedSDMCState *s)
/* use a common default */
warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
s->ram_size);
- s->ram_size = 256 << 20;
+ s->ram_size = 256 * M_BYTE;
return ASPEED_SDMC_DRAM_256MB;
}
static int ast2500_rambits(AspeedSDMCState *s)
{
- switch (s->ram_size >> 20) {
+ switch (s->ram_size / M_BYTE) {
case 128:
return ASPEED_SDMC_AST2500_128MB;
case 256:
@@ -187,7 +187,7 @@ static int ast2500_rambits(AspeedSDMCState *s)
/* use a common default */
warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
s->ram_size);
- s->ram_size = 512 << 20;
+ s->ram_size = 512 * M_BYTE;
return ASPEED_SDMC_AST2500_512MB;
}
diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c
index c2a9df29c6..3d46bdbd09 100644
--- a/hw/misc/imx7_gpr.c
+++ b/hw/misc/imx7_gpr.c
@@ -98,7 +98,7 @@ static void imx7_gpr_init(Object *obj)
IMX7GPRState *s = IMX7_GPR(obj);
memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,
- TYPE_IMX7_GPR, 64 * 1024);
+ TYPE_IMX7_GPR, 64 * K_BYTE);
sysbus_init_mmio(sd, &s->mmio);
}
diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
index 84f9e4c612..af6b620e3e 100644
--- a/hw/misc/omap_gpmc.c
+++ b/hw/misc/omap_gpmc.c
@@ -850,11 +850,11 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
&omap_nand_ops,
&s->cs_file[cs],
"omap-nand",
- 256 * 1024 * 1024);
+ 256 * M_BYTE);
}
memory_region_init_io(&s->prefetch.iomem, NULL, &omap_prefetch_ops, s,
- "omap-gpmc-prefetch", 256 * 1024 * 1024);
+ "omap-gpmc-prefetch", 256 * M_BYTE);
return s;
}
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 5059396bc6..b51cb6c0a9 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -149,35 +149,35 @@
* Segment Address Registers.
*/
static const AspeedSegments aspeed_segments_legacy[] = {
- { 0x10000000, 32 * 1024 * 1024 },
+ { 0x10000000, 32 * M_BYTE },
};
static const AspeedSegments aspeed_segments_fmc[] = {
- { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
- { 0x24000000, 32 * 1024 * 1024 },
- { 0x26000000, 32 * 1024 * 1024 },
- { 0x28000000, 32 * 1024 * 1024 },
- { 0x2A000000, 32 * 1024 * 1024 }
+ { 0x20000000, 64 * M_BYTE }, /* start address is readonly */
+ { 0x24000000, 32 * M_BYTE },
+ { 0x26000000, 32 * M_BYTE },
+ { 0x28000000, 32 * M_BYTE },
+ { 0x2A000000, 32 * M_BYTE }
};
static const AspeedSegments aspeed_segments_spi[] = {
- { 0x30000000, 64 * 1024 * 1024 },
+ { 0x30000000, 64 * M_BYTE },
};
static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
- { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
- { 0x28000000, 32 * 1024 * 1024 },
- { 0x2A000000, 32 * 1024 * 1024 },
+ { 0x20000000, 128 * M_BYTE }, /* start address is readonly */
+ { 0x28000000, 32 * M_BYTE },
+ { 0x2A000000, 32 * M_BYTE },
};
static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
- { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
- { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
+ { 0x30000000, 32 * M_BYTE }, /* start address is readonly */
+ { 0x32000000, 96 * M_BYTE }, /* end address is readonly */
};
static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
- { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
- { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
+ { 0x38000000, 32 * M_BYTE }, /* start address is readonly */
+ { 0x3A000000, 96 * M_BYTE }, /* end address is readonly */
};
static const AspeedSMCController controllers[] = {
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v2 07/30] hw/arm: use the BYTE-based definitions
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 07/30] hw/arm: " Philippe Mathieu-Daudé
@ 2018-03-06 15:46 ` Alex Bennée
0 siblings, 0 replies; 40+ messages in thread
From: Alex Bennée @ 2018-03-06 15:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-trivial, Peter Maydell, Peter Crosthwaite, Alistair Francis,
qemu-devel, open list:ARM, Jan Kiszka, Antony Pavlov,
Edgar E. Iglesias, Peter Chubb
Philippe Mathieu-Daudé <f4bug@amsat.org> writes:
> It eases code review, unit is explicit.
>
> Patch generated using:
>
> $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
>
> and modified manually.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/arm/stm32f205_soc.h | 4 ++--
> hw/arm/boot.c | 6 +++---
> hw/arm/collie.c | 4 ++--
> hw/arm/digic_boards.c | 6 +++---
> hw/arm/gumstix.c | 2 +-
> hw/arm/integratorcp.c | 2 +-
> hw/arm/mainstone.c | 2 +-
> hw/arm/musicpal.c | 8 ++++----
> hw/arm/omap_sx1.c | 8 ++++----
> hw/arm/raspi.c | 4 ++--
> hw/arm/stellaris.c | 4 ++--
> hw/arm/versatilepb.c | 4 ++--
> hw/arm/vexpress.c | 6 +++---
> hw/arm/virt.c | 4 ++--
> hw/arm/xilinx_zynq.c | 4 ++--
> hw/misc/aspeed_sdmc.c | 8 ++++----
> hw/misc/imx7_gpr.c | 2 +-
> hw/misc/omap_gpmc.c | 4 ++--
> hw/ssi/aspeed_smc.c | 28 ++++++++++++++--------------
> 19 files changed, 55 insertions(+), 55 deletions(-)
>
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 922a733f88..e30ae33c65 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -43,9 +43,9 @@
> #define STM_NUM_SPIS 3
>
> #define FLASH_BASE_ADDRESS 0x08000000
> -#define FLASH_SIZE (1024 * 1024)
> +#define FLASH_SIZE (1 * M_BYTE)
> #define SRAM_BASE_ADDRESS 0x20000000
> -#define SRAM_SIZE (128 * 1024)
> +#define SRAM_SIZE (128 * K_BYTE)
>
> typedef struct STM32F205State {
> /*< private >*/
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index 6d0c92ab88..51df96a6c8 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -1015,7 +1015,7 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
> * the initrd at 128MB.
> */
> info->initrd_start = info->loader_start +
> - MIN(info->ram_size / 2, 128 * 1024 * 1024);
> + MIN(info->ram_size / 2, 128 * M_BYTE);
>
> /* Assume that raw images are linux kernels, and ELF images are not. */
> kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,
> @@ -1102,13 +1102,13 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
> *
> * Let's play safe and prealign it to 2MB to give us some space.
> */
> - align = 2 * 1024 * 1024;
> + align = 2 * M_BYTE;
> } else {
> /*
> * Some 32bit kernels will trash anything in the 4K page the
> * initrd ends in, so make sure the DTB isn't caught up in that.
> */
> - align = 4096;
> + align = 4 * K_BYTE;
> }
>
> /* Place the DTB after the initrd in memory with alignment. */
> diff --git a/hw/arm/collie.c b/hw/arm/collie.c
> index f8c566e2e5..1695863629 100644
> --- a/hw/arm/collie.c
> +++ b/hw/arm/collie.c
> @@ -39,12 +39,12 @@ static void collie_init(MachineState *machine)
> dinfo = drive_get(IF_PFLASH, 0, 0);
> pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
> dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
> - (64 * 1024), 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
> + 64 * K_BYTE, 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
>
> dinfo = drive_get(IF_PFLASH, 0, 1);
> pflash_cfi01_register(SA_CS1, NULL, "collie.fl2", 0x02000000,
> dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
> - (64 * 1024), 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
> + 64 * K_BYTE, 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
>
> sysbus_create_simple("scoop", 0x40800000, NULL);
>
> diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
> index 9f11dcd11f..04e52e776f 100644
> --- a/hw/arm/digic_boards.c
> +++ b/hw/arm/digic_boards.c
> @@ -126,8 +126,8 @@ static void digic_load_rom(DigicBoardState *s, hwaddr addr,
> static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
> const char *def_filename)
> {
> -#define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024)
> -#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024)
> +#define FLASH_K8P3215UQB_SIZE (4 * M_BYTE)
> +#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * K_BYTE)
>
> pflash_cfi02_register(addr, NULL, "pflash", FLASH_K8P3215UQB_SIZE,
> NULL, FLASH_K8P3215UQB_SECTOR_SIZE,
> @@ -141,7 +141,7 @@ static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
> }
>
> static DigicBoard digic4_board_canon_a1100 = {
> - .ram_size = 64 * 1024 * 1024,
> + .ram_size = 64 * M_BYTE,
> .add_rom1 = digic4_add_k8p3215uqb_rom,
> .rom1_def_filename = "canon-a1100-rom1.bin",
> };
> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
> index ea2a3c532d..fc15df1d12 100644
> --- a/hw/arm/gumstix.c
> +++ b/hw/arm/gumstix.c
> @@ -47,7 +47,7 @@
> #include "sysemu/qtest.h"
> #include "cpu.h"
>
> -static const int sector_len = 128 * 1024;
> +static const int sector_len = 128 * K_BYTE;
>
> static void connex_init(MachineState *machine)
> {
> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
> index e8303b83be..4e711194ef 100644
> --- a/hw/arm/integratorcp.c
> +++ b/hw/arm/integratorcp.c
> @@ -609,7 +609,7 @@ static void integratorcp_init(MachineState *machine)
> memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
>
> dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
> - qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
> + qdev_prop_set_uint32(dev, "memsz", ram_size / M_BYTE);
> qdev_init_nofail(dev);
> sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
>
> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
> index 4215c025fc..37c21ed6d0 100644
> --- a/hw/arm/mainstone.c
> +++ b/hw/arm/mainstone.c
> @@ -115,7 +115,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
> MachineState *machine,
> enum mainstone_model_e model, int arm_id)
> {
> - uint32_t sector_len = 256 * 1024;
> + uint32_t sector_len = 256 * K_BYTE;
> hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
> PXA2xxState *mpu;
> DeviceState *mst_irq;
> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
> index 38d7322a19..d6d1ce75c5 100644
> --- a/hw/arm/musicpal.c
> +++ b/hw/arm/musicpal.c
> @@ -62,8 +62,8 @@
> #define MP_SRAM_BASE 0xC0000000
> #define MP_SRAM_SIZE 0x00020000
>
> -#define MP_RAM_DEFAULT_SIZE 32*1024*1024
> -#define MP_FLASH_SIZE_MAX 32*1024*1024
> +#define MP_RAM_DEFAULT_SIZE (32 * M_BYTE)
> +#define MP_FLASH_SIZE_MAX (32 * M_BYTE)
>
> #define MP_TIMER1_IRQ 4
> #define MP_TIMER2_IRQ 5
> @@ -1625,8 +1625,8 @@ static void musicpal_init(MachineState *machine)
> BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
>
> flash_size = blk_getlength(blk);
> - if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
> - flash_size != 32*1024*1024) {
> + if (flash_size != 8 * M_BYTE && flash_size != 16 * M_BYTE &&
> + flash_size != 32 * M_BYTE) {
> error_report("Invalid flash image size");
> exit(1);
> }
> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
> index eccc19c77b..729af8bb80 100644
> --- a/hw/arm/omap_sx1.c
> +++ b/hw/arm/omap_sx1.c
> @@ -88,10 +88,10 @@ static const MemoryRegionOps static_ops = {
> };
>
> #define sdram_size 0x02000000
> -#define sector_size (128 * 1024)
> -#define flash0_size (16 * 1024 * 1024)
> -#define flash1_size ( 8 * 1024 * 1024)
> -#define flash2_size (32 * 1024 * 1024)
> +#define sector_size (128 * K_BYTE)
> +#define flash0_size (16 * M_BYTE)
> +#define flash1_size (8 * M_BYTE)
> +#define flash2_size (32 * M_BYTE)
> #define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
> #define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
>
> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> index a37881433c..4b54fa5ad4 100644
> --- a/hw/arm/raspi.c
> +++ b/hw/arm/raspi.c
> @@ -183,7 +183,7 @@ static void raspi2_machine_init(MachineClass *mc)
> mc->max_cpus = BCM2836_NCPUS;
> mc->min_cpus = BCM2836_NCPUS;
> mc->default_cpus = BCM2836_NCPUS;
> - mc->default_ram_size = 1024 * 1024 * 1024;
> + mc->default_ram_size = 1 * G_BYTE;
> mc->ignore_memory_transaction_failures = true;
> };
> DEFINE_MACHINE("raspi2", raspi2_machine_init)
> @@ -206,7 +206,7 @@ static void raspi3_machine_init(MachineClass *mc)
> mc->max_cpus = BCM2836_NCPUS;
> mc->min_cpus = BCM2836_NCPUS;
> mc->default_cpus = BCM2836_NCPUS;
> - mc->default_ram_size = 1024 * 1024 * 1024;
> + mc->default_ram_size = 1 * G_BYTE;
> }
> DEFINE_MACHINE("raspi3", raspi3_machine_init)
> #endif
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index de7c0fc4a6..8ff7567126 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -1284,8 +1284,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> MemoryRegion *flash = g_new(MemoryRegion, 1);
> MemoryRegion *system_memory = get_system_memory();
>
> - flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
> - sram_size = ((board->dc0 >> 18) + 1) * 1024;
> + flash_size = (((board->dc0 & 0xffff) + 1) << 1) * K_BYTE;
> + sram_size = ((board->dc0 >> 18) + 1) * K_BYTE;
>
> /* Flash programming is done via the SCU, so pretend it is ROM. */
> memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
> diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
> index 418792cd02..041f12beb7 100644
> --- a/hw/arm/versatilepb.c
> +++ b/hw/arm/versatilepb.c
> @@ -26,8 +26,8 @@
> #include "hw/char/pl011.h"
>
> #define VERSATILE_FLASH_ADDR 0x34000000
> -#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
> -#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
> +#define VERSATILE_FLASH_SIZE (64 * M_BYTE)
> +#define VERSATILE_FLASH_SECT_SIZE (256 * K_BYTE)
>
> /* Primary interrupt controller. */
>
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index 9fad79177a..7b12dfca41 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -45,8 +45,8 @@
> #include "hw/cpu/a15mpcore.h"
>
> #define VEXPRESS_BOARD_ID 0x8e0
> -#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
> -#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
> +#define VEXPRESS_FLASH_SIZE (64 * M_BYTE)
> +#define VEXPRESS_FLASH_SECT_SIZE (256 * K_BYTE)
>
> /* Number of virtio transports to create (0..8; limited by
> * number of available IRQ lines).
> @@ -355,7 +355,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
> * warning if we are on a host where ram_addr_t is 32 bits.
> */
> uint64_t rsz = ram_size;
> - if (rsz > (30ULL * 1024 * 1024 * 1024)) {
> + if (rsz > 30 * G_BYTE) {
> error_report("vexpress-a15: cannot model more than 30GB RAM");
> exit(1);
> }
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index dbb3c8036a..8202a428e0 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -110,7 +110,7 @@ static ARMPlatformBusSystemParams platform_bus_params;
> * terabyte of physical address space.)
> */
> #define RAMLIMIT_GB 255
> -#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
> +#define RAMLIMIT_BYTES (RAMLIMIT_GB * G_BYTE)
>
> /* Addresses and sizes of our components.
> * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
> @@ -783,7 +783,7 @@ static void create_one_flash(const char *name, hwaddr flashbase,
> DriveInfo *dinfo = drive_get_next(IF_PFLASH);
> DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> - const uint64_t sectorlength = 256 * 1024;
> + const uint64_t sectorlength = 256 * K_BYTE;
>
> if (dinfo) {
> qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 0f76333770..7a68503e68 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -40,8 +40,8 @@
> #define NUM_QSPI_FLASHES 2
> #define NUM_QSPI_BUSSES 2
>
> -#define FLASH_SIZE (64 * 1024 * 1024)
> -#define FLASH_SECTOR_SIZE (128 * 1024)
> +#define FLASH_SIZE (64 * M_BYTE)
> +#define FLASH_SECTOR_SIZE (128 * K_BYTE)
>
> #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
>
> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
> index 0df008e52a..eaf090b7b1 100644
> --- a/hw/misc/aspeed_sdmc.c
> +++ b/hw/misc/aspeed_sdmc.c
> @@ -149,7 +149,7 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
>
> static int ast2400_rambits(AspeedSDMCState *s)
> {
> - switch (s->ram_size >> 20) {
> + switch (s->ram_size / M_BYTE) {
> case 64:
> return ASPEED_SDMC_DRAM_64MB;
> case 128:
> @@ -165,13 +165,13 @@ static int ast2400_rambits(AspeedSDMCState *s)
> /* use a common default */
> warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
> s->ram_size);
> - s->ram_size = 256 << 20;
> + s->ram_size = 256 * M_BYTE;
> return ASPEED_SDMC_DRAM_256MB;
> }
>
> static int ast2500_rambits(AspeedSDMCState *s)
> {
> - switch (s->ram_size >> 20) {
> + switch (s->ram_size / M_BYTE) {
> case 128:
> return ASPEED_SDMC_AST2500_128MB;
> case 256:
> @@ -187,7 +187,7 @@ static int ast2500_rambits(AspeedSDMCState *s)
> /* use a common default */
> warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
> s->ram_size);
> - s->ram_size = 512 << 20;
> + s->ram_size = 512 * M_BYTE;
> return ASPEED_SDMC_AST2500_512MB;
> }
>
> diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c
> index c2a9df29c6..3d46bdbd09 100644
> --- a/hw/misc/imx7_gpr.c
> +++ b/hw/misc/imx7_gpr.c
> @@ -98,7 +98,7 @@ static void imx7_gpr_init(Object *obj)
> IMX7GPRState *s = IMX7_GPR(obj);
>
> memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,
> - TYPE_IMX7_GPR, 64 * 1024);
> + TYPE_IMX7_GPR, 64 * K_BYTE);
> sysbus_init_mmio(sd, &s->mmio);
> }
>
> diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
> index 84f9e4c612..af6b620e3e 100644
> --- a/hw/misc/omap_gpmc.c
> +++ b/hw/misc/omap_gpmc.c
> @@ -850,11 +850,11 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
> &omap_nand_ops,
> &s->cs_file[cs],
> "omap-nand",
> - 256 * 1024 * 1024);
> + 256 * M_BYTE);
> }
>
> memory_region_init_io(&s->prefetch.iomem, NULL, &omap_prefetch_ops, s,
> - "omap-gpmc-prefetch", 256 * 1024 * 1024);
> + "omap-gpmc-prefetch", 256 * M_BYTE);
> return s;
> }
>
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 5059396bc6..b51cb6c0a9 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -149,35 +149,35 @@
> * Segment Address Registers.
> */
> static const AspeedSegments aspeed_segments_legacy[] = {
> - { 0x10000000, 32 * 1024 * 1024 },
> + { 0x10000000, 32 * M_BYTE },
> };
>
> static const AspeedSegments aspeed_segments_fmc[] = {
> - { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
> - { 0x24000000, 32 * 1024 * 1024 },
> - { 0x26000000, 32 * 1024 * 1024 },
> - { 0x28000000, 32 * 1024 * 1024 },
> - { 0x2A000000, 32 * 1024 * 1024 }
> + { 0x20000000, 64 * M_BYTE }, /* start address is readonly */
> + { 0x24000000, 32 * M_BYTE },
> + { 0x26000000, 32 * M_BYTE },
> + { 0x28000000, 32 * M_BYTE },
> + { 0x2A000000, 32 * M_BYTE }
> };
>
> static const AspeedSegments aspeed_segments_spi[] = {
> - { 0x30000000, 64 * 1024 * 1024 },
> + { 0x30000000, 64 * M_BYTE },
> };
>
> static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
> - { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
> - { 0x28000000, 32 * 1024 * 1024 },
> - { 0x2A000000, 32 * 1024 * 1024 },
> + { 0x20000000, 128 * M_BYTE }, /* start address is readonly */
> + { 0x28000000, 32 * M_BYTE },
> + { 0x2A000000, 32 * M_BYTE },
> };
>
> static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
> - { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
> - { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
> + { 0x30000000, 32 * M_BYTE }, /* start address is readonly */
> + { 0x32000000, 96 * M_BYTE }, /* end address is readonly */
> };
>
> static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
> - { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
> - { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
> + { 0x38000000, 32 * M_BYTE }, /* start address is readonly */
> + { 0x3A000000, 96 * M_BYTE }, /* end address is readonly */
> };
>
> static const AspeedSMCController controllers[] = {
--
Alex Bennée
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v2 08/30] hw/i386: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 07/30] hw/arm: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 18:51 ` Anthony PERARD
2018-03-06 12:43 ` Igor Mammedov
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 09/30] hw/sparc: " Philippe Mathieu-Daudé
` (21 subsequent siblings)
29 siblings, 2 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Michael S. Tsirkin,
Igor Mammedov, Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Stefano Stabellini, Anthony Perard,
open list:X86
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/i386/ich9.h | 2 +-
hw/i386/acpi-build.c | 4 ++--
hw/i386/pc.c | 18 +++++++++---------
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
hw/i386/pc_sysfw.c | 8 ++++----
hw/i386/xen/xen-mapcache.c | 2 +-
hw/intc/apic_common.c | 2 +-
hw/pci-host/gpex.c | 2 +-
hw/pci-host/piix.c | 4 ++--
hw/pci-host/q35.c | 16 ++++++++--------
11 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 673d13d28f..87628dd867 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -22,7 +22,7 @@ I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
void ich9_generate_smi(void);
-#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
+#define ICH9_CC_SIZE (16 * K_BYTE) /* Chipset configuration registers */
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
#define ICH9_LPC_DEVICE(obj) \
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index deb440f286..9ccc6192b5 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2320,8 +2320,8 @@ build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
(void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
}
-#define HOLE_640K_START (640 * 1024)
-#define HOLE_640K_END (1024 * 1024)
+#define HOLE_640K_START (640 * K_BYTE)
+#define HOLE_640K_END (1024 * K_BYTE)
static void
build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 55e69d66fe..94a1f3bc7b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -452,8 +452,8 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
- if (pcms->below_4g_mem_size > 1024 * 1024) {
- val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
+ if (pcms->below_4g_mem_size > 1 * M_BYTE) {
+ val = (pcms->below_4g_mem_size - 1 * M_BYTE) / 1024;
} else {
val = 0;
}
@@ -464,8 +464,8 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
- if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
- val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
+ if (pcms->below_4g_mem_size > 16 * M_BYTE) {
+ val = (pcms->below_4g_mem_size - 16 * M_BYTE) / 65536;
} else {
val = 0;
}
@@ -1390,11 +1390,11 @@ void pc_memory_init(PCMachineState *pcms,
}
pcms->hotplug_memory.base =
- ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
+ ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, G_BYTE);
if (pcmc->enforce_aligned_dimm) {
/* size hotplug region assuming 1G page max alignment per slot */
- hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
+ hotplug_mem_size += machine->ram_slots * G_BYTE;
}
if ((pcms->hotplug_memory.base + hotplug_mem_size) <
@@ -1436,7 +1436,7 @@ void pc_memory_init(PCMachineState *pcms,
if (!pcmc->broken_reserved_end) {
res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
}
- *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
+ *val = cpu_to_le64(ROUND_UP(res_mem_end, G_BYTE));
fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
}
@@ -1472,7 +1472,7 @@ uint64_t pc_pci_hole64_start(void)
hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
}
- return ROUND_UP(hole64_start, 1ULL << 30);
+ return ROUND_UP(hole64_start, G_BYTE);
}
qemu_irq pc_allocate_cpu_irq(void)
@@ -2114,7 +2114,7 @@ static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
return;
}
- if (value < (1ULL << 20)) {
+ if (value < 1 * M_BYTE) {
warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
"BIOS may not work with less than 1MiB", value);
}
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 456dc9e9f0..975dfc848e 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -131,7 +131,7 @@ static void pc_init1(MachineState *machine,
if (lowmem > 0xc0000000) {
lowmem = 0xc0000000;
}
- if (lowmem & ((1ULL << 30) - 1)) {
+ if (lowmem & ((1 * G_BYTE) - 1)) {
warn_report("Large machine and max_ram_below_4g "
"(%" PRIu64 ") not a multiple of 1G; "
"possible bad performance.",
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index aba7541a82..79b84bc559 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -104,7 +104,7 @@ static void pc_q35_init(MachineState *machine)
if (lowmem > pcms->max_ram_below_4g) {
lowmem = pcms->max_ram_below_4g;
if (machine->ram_size - lowmem > lowmem &&
- lowmem & ((1ULL << 30) - 1)) {
+ lowmem & ((1 * G_BYTE) - 1)) {
warn_report("There is possibly poor performance as the ram size "
" (0x%" PRIx64 ") is more then twice the size of"
" max-ram-below-4g (%"PRIu64") and"
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
index 4325575e7d..97488a832d 100644
--- a/hw/i386/pc_sysfw.c
+++ b/hw/i386/pc_sysfw.c
@@ -56,7 +56,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
flash_size = memory_region_size(flash_mem);
/* map the last 128KB of the BIOS in ISA space */
- isa_bios_size = MIN(flash_size, 128 * 1024);
+ isa_bios_size = MIN(flash_size, 128 * K_BYTE);
isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size,
&error_fatal);
@@ -83,7 +83,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
* only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
* size.
*/
-#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8*1024*1024))
+#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8 * M_BYTE))
/* This function maps flash drives from 4G downward, in order of their unit
* numbers. The mapping starts at unit#0, with unit number increments of 1, and
@@ -209,8 +209,8 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
/* map the last 128KB of the BIOS in ISA space */
isa_bios_size = bios_size;
- if (isa_bios_size > (128 * 1024)) {
- isa_bios_size = 128 * 1024;
+ if (isa_bios_size > 128 * K_BYTE) {
+ isa_bios_size = 128 * K_BYTE;
}
isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
index efa35dc6e0..5f48fde799 100644
--- a/hw/i386/xen/xen-mapcache.c
+++ b/hw/i386/xen/xen-mapcache.c
@@ -47,7 +47,7 @@
* From empirical tests I observed that qemu use 75MB more than the
* max_mcache_size.
*/
-#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024)
+#define NON_MCACHE_MEMORY_SIZE (80 * M_BYTE)
typedef struct MapCacheEntry {
hwaddr paddr_index;
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index 78903ea909..3a6c297c52 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -319,7 +319,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
- !hax_enabled() && ram_size >= 1024 * 1024) {
+ !hax_enabled() && ram_size >= 1 * M_BYTE) {
vapic = sysbus_create_simple("kvmvapic", -1, NULL);
}
s->vapic = vapic;
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index 2583b151a4..9cab9d0e7d 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -79,7 +79,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
- memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
+ memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * K_BYTE);
sysbus_init_mmio(sbd, &pex->mmio);
sysbus_init_mmio(sbd, &s->io_mmio);
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 0e608347c1..7fc1822ec0 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -284,7 +284,7 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
pci_bus_get_w64_range(h->bus, &w64);
value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
- hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
+ hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, G_BYTE);
if (s->pci_hole64_fix && value < hole64_end) {
value = hole64_end;
}
@@ -430,7 +430,7 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
*piix3_devfn = piix3->dev.devfn;
- ram_size = ram_size / 8 / 1024 / 1024;
+ ram_size /= 8 * M_BYTE;
if (ram_size > 255) {
ram_size = 255;
}
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index a36a1195e4..a54b6736e5 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -144,7 +144,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
pci_bus_get_w64_range(h->bus, &w64);
value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
- hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
+ hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, G_BYTE);
if (s->pci_hole64_fix && value < hole64_end) {
value = hole64_end;
}
@@ -310,15 +310,15 @@ static void mch_update_pciexbar(MCHPCIState *mch)
addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
- length = 256 * 1024 * 1024;
+ length = 256 * M_BYTE;
break;
case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
- length = 128 * 1024 * 1024;
+ length = 128 * M_BYTE;
addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
break;
case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
- length = 64 * 1024 * 1024;
+ length = 64 * M_BYTE;
addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
break;
case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
@@ -396,16 +396,16 @@ static void mch_update_smram(MCHPCIState *mch)
switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
- tseg_size = 1024 * 1024;
+ tseg_size = 1 * M_BYTE;
break;
case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
- tseg_size = 1024 * 1024 * 2;
+ tseg_size = 2 * M_BYTE;
break;
case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
- tseg_size = 1024 * 1024 * 8;
+ tseg_size = 8 * M_BYTE;
break;
default:
- tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
+ tseg_size = (uint32_t)mch->ext_tseg_mbytes * M_BYTE;
break;
}
} else {
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v2 08/30] hw/i386: use the BYTE-based definitions
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 08/30] hw/i386: " Philippe Mathieu-Daudé
@ 2018-03-05 18:51 ` Anthony PERARD
2018-03-06 12:43 ` Igor Mammedov
1 sibling, 0 replies; 40+ messages in thread
From: Anthony PERARD @ 2018-03-05 18:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-trivial, qemu-devel, Michael S. Tsirkin, Igor Mammedov,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Stefano Stabellini, open list:X86
On Mon, Mar 05, 2018 at 08:27:10AM -0300, Philippe Mathieu-Daudé wrote:
> It eases code review, unit is explicit.
>
> Patch generated using:
>
> $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
>
> and modified manually.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/i386/xen/xen-mapcache.c | 2 +-
>
> diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
> index efa35dc6e0..5f48fde799 100644
> --- a/hw/i386/xen/xen-mapcache.c
> +++ b/hw/i386/xen/xen-mapcache.c
> @@ -47,7 +47,7 @@
> * From empirical tests I observed that qemu use 75MB more than the
> * max_mcache_size.
> */
> -#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024)
> +#define NON_MCACHE_MEMORY_SIZE (80 * M_BYTE)
>
> typedef struct MapCacheEntry {
> hwaddr paddr_index;
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
--
Anthony PERARD
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v2 08/30] hw/i386: use the BYTE-based definitions
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 08/30] hw/i386: " Philippe Mathieu-Daudé
2018-03-05 18:51 ` Anthony PERARD
@ 2018-03-06 12:43 ` Igor Mammedov
1 sibling, 0 replies; 40+ messages in thread
From: Igor Mammedov @ 2018-03-06 12:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-trivial, Stefano Stabellini, Eduardo Habkost,
Michael S. Tsirkin, qemu-devel, Anthony Perard, Paolo Bonzini,
Marcel Apfelbaum, open list:X86, Richard Henderson
On Mon, 5 Mar 2018 08:27:10 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> It eases code review, unit is explicit.
>
> Patch generated using:
>
> $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
>
> and modified manually.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
My apologies,
compilation errors were my mistake of not applying 1-2/30 patches first.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> include/hw/i386/ich9.h | 2 +-
> hw/i386/acpi-build.c | 4 ++--
> hw/i386/pc.c | 18 +++++++++---------
> hw/i386/pc_piix.c | 2 +-
> hw/i386/pc_q35.c | 2 +-
> hw/i386/pc_sysfw.c | 8 ++++----
> hw/i386/xen/xen-mapcache.c | 2 +-
> hw/intc/apic_common.c | 2 +-
> hw/pci-host/gpex.c | 2 +-
> hw/pci-host/piix.c | 4 ++--
> hw/pci-host/q35.c | 16 ++++++++--------
> 11 files changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> index 673d13d28f..87628dd867 100644
> --- a/include/hw/i386/ich9.h
> +++ b/include/hw/i386/ich9.h
> @@ -22,7 +22,7 @@ I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
>
> void ich9_generate_smi(void);
>
> -#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
> +#define ICH9_CC_SIZE (16 * K_BYTE) /* Chipset configuration registers */
>
> #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
> #define ICH9_LPC_DEVICE(obj) \
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index deb440f286..9ccc6192b5 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -2320,8 +2320,8 @@ build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
> (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
> }
>
> -#define HOLE_640K_START (640 * 1024)
> -#define HOLE_640K_END (1024 * 1024)
> +#define HOLE_640K_START (640 * K_BYTE)
> +#define HOLE_640K_END (1024 * K_BYTE)
>
> static void
> build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 55e69d66fe..94a1f3bc7b 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -452,8 +452,8 @@ void pc_cmos_init(PCMachineState *pcms,
> rtc_set_memory(s, 0x15, val);
> rtc_set_memory(s, 0x16, val >> 8);
> /* extended memory (next 64MiB) */
> - if (pcms->below_4g_mem_size > 1024 * 1024) {
> - val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
> + if (pcms->below_4g_mem_size > 1 * M_BYTE) {
> + val = (pcms->below_4g_mem_size - 1 * M_BYTE) / 1024;
> } else {
> val = 0;
> }
> @@ -464,8 +464,8 @@ void pc_cmos_init(PCMachineState *pcms,
> rtc_set_memory(s, 0x30, val);
> rtc_set_memory(s, 0x31, val >> 8);
> /* memory between 16MiB and 4GiB */
> - if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
> - val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
> + if (pcms->below_4g_mem_size > 16 * M_BYTE) {
> + val = (pcms->below_4g_mem_size - 16 * M_BYTE) / 65536;
> } else {
> val = 0;
> }
> @@ -1390,11 +1390,11 @@ void pc_memory_init(PCMachineState *pcms,
> }
>
> pcms->hotplug_memory.base =
> - ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
> + ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, G_BYTE);
>
> if (pcmc->enforce_aligned_dimm) {
> /* size hotplug region assuming 1G page max alignment per slot */
> - hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
> + hotplug_mem_size += machine->ram_slots * G_BYTE;
> }
>
> if ((pcms->hotplug_memory.base + hotplug_mem_size) <
> @@ -1436,7 +1436,7 @@ void pc_memory_init(PCMachineState *pcms,
> if (!pcmc->broken_reserved_end) {
> res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
> }
> - *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
> + *val = cpu_to_le64(ROUND_UP(res_mem_end, G_BYTE));
> fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
> }
>
> @@ -1472,7 +1472,7 @@ uint64_t pc_pci_hole64_start(void)
> hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
> }
>
> - return ROUND_UP(hole64_start, 1ULL << 30);
> + return ROUND_UP(hole64_start, G_BYTE);
> }
>
> qemu_irq pc_allocate_cpu_irq(void)
> @@ -2114,7 +2114,7 @@ static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
> return;
> }
>
> - if (value < (1ULL << 20)) {
> + if (value < 1 * M_BYTE) {
> warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
> "BIOS may not work with less than 1MiB", value);
> }
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 456dc9e9f0..975dfc848e 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -131,7 +131,7 @@ static void pc_init1(MachineState *machine,
> if (lowmem > 0xc0000000) {
> lowmem = 0xc0000000;
> }
> - if (lowmem & ((1ULL << 30) - 1)) {
> + if (lowmem & ((1 * G_BYTE) - 1)) {
> warn_report("Large machine and max_ram_below_4g "
> "(%" PRIu64 ") not a multiple of 1G; "
> "possible bad performance.",
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index aba7541a82..79b84bc559 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -104,7 +104,7 @@ static void pc_q35_init(MachineState *machine)
> if (lowmem > pcms->max_ram_below_4g) {
> lowmem = pcms->max_ram_below_4g;
> if (machine->ram_size - lowmem > lowmem &&
> - lowmem & ((1ULL << 30) - 1)) {
> + lowmem & ((1 * G_BYTE) - 1)) {
> warn_report("There is possibly poor performance as the ram size "
> " (0x%" PRIx64 ") is more then twice the size of"
> " max-ram-below-4g (%"PRIu64") and"
> diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
> index 4325575e7d..97488a832d 100644
> --- a/hw/i386/pc_sysfw.c
> +++ b/hw/i386/pc_sysfw.c
> @@ -56,7 +56,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
> flash_size = memory_region_size(flash_mem);
>
> /* map the last 128KB of the BIOS in ISA space */
> - isa_bios_size = MIN(flash_size, 128 * 1024);
> + isa_bios_size = MIN(flash_size, 128 * K_BYTE);
> isa_bios = g_malloc(sizeof(*isa_bios));
> memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size,
> &error_fatal);
> @@ -83,7 +83,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
> * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
> * size.
> */
> -#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8*1024*1024))
> +#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8 * M_BYTE))
>
> /* This function maps flash drives from 4G downward, in order of their unit
> * numbers. The mapping starts at unit#0, with unit number increments of 1, and
> @@ -209,8 +209,8 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
>
> /* map the last 128KB of the BIOS in ISA space */
> isa_bios_size = bios_size;
> - if (isa_bios_size > (128 * 1024)) {
> - isa_bios_size = 128 * 1024;
> + if (isa_bios_size > 128 * K_BYTE) {
> + isa_bios_size = 128 * K_BYTE;
> }
> isa_bios = g_malloc(sizeof(*isa_bios));
> memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
> diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
> index efa35dc6e0..5f48fde799 100644
> --- a/hw/i386/xen/xen-mapcache.c
> +++ b/hw/i386/xen/xen-mapcache.c
> @@ -47,7 +47,7 @@
> * From empirical tests I observed that qemu use 75MB more than the
> * max_mcache_size.
> */
> -#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024)
> +#define NON_MCACHE_MEMORY_SIZE (80 * M_BYTE)
>
> typedef struct MapCacheEntry {
> hwaddr paddr_index;
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index 78903ea909..3a6c297c52 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -319,7 +319,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
>
> /* Note: We need at least 1M to map the VAPIC option ROM */
> if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
> - !hax_enabled() && ram_size >= 1024 * 1024) {
> + !hax_enabled() && ram_size >= 1 * M_BYTE) {
> vapic = sysbus_create_simple("kvmvapic", -1, NULL);
> }
> s->vapic = vapic;
> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
> index 2583b151a4..9cab9d0e7d 100644
> --- a/hw/pci-host/gpex.c
> +++ b/hw/pci-host/gpex.c
> @@ -79,7 +79,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
>
> pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
> memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
> - memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
> + memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * K_BYTE);
>
> sysbus_init_mmio(sbd, &pex->mmio);
> sysbus_init_mmio(sbd, &s->io_mmio);
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 0e608347c1..7fc1822ec0 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -284,7 +284,7 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
>
> pci_bus_get_w64_range(h->bus, &w64);
> value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
> - hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
> + hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, G_BYTE);
> if (s->pci_hole64_fix && value < hole64_end) {
> value = hole64_end;
> }
> @@ -430,7 +430,7 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>
> *piix3_devfn = piix3->dev.devfn;
>
> - ram_size = ram_size / 8 / 1024 / 1024;
> + ram_size /= 8 * M_BYTE;
> if (ram_size > 255) {
> ram_size = 255;
> }
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index a36a1195e4..a54b6736e5 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -144,7 +144,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
>
> pci_bus_get_w64_range(h->bus, &w64);
> value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
> - hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
> + hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, G_BYTE);
> if (s->pci_hole64_fix && value < hole64_end) {
> value = hole64_end;
> }
> @@ -310,15 +310,15 @@ static void mch_update_pciexbar(MCHPCIState *mch)
> addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
> switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
> case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
> - length = 256 * 1024 * 1024;
> + length = 256 * M_BYTE;
> break;
> case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
> - length = 128 * 1024 * 1024;
> + length = 128 * M_BYTE;
> addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
> MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
> break;
> case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
> - length = 64 * 1024 * 1024;
> + length = 64 * M_BYTE;
> addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
> break;
> case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
> @@ -396,16 +396,16 @@ static void mch_update_smram(MCHPCIState *mch)
> switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
> MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
> case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
> - tseg_size = 1024 * 1024;
> + tseg_size = 1 * M_BYTE;
> break;
> case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
> - tseg_size = 1024 * 1024 * 2;
> + tseg_size = 2 * M_BYTE;
> break;
> case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
> - tseg_size = 1024 * 1024 * 8;
> + tseg_size = 8 * M_BYTE;
> break;
> default:
> - tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
> + tseg_size = (uint32_t)mch->ext_tseg_mbytes * M_BYTE;
> break;
> }
> } else {
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v2 09/30] hw/sparc: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 08/30] hw/i386: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 10/30] hw/ppc: " Philippe Mathieu-Daudé
` (20 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Fabien Chouteau,
Mark Cave-Ayland, Artyom Tarasenko
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sparc/leon3.c | 8 ++++----
hw/sparc/sun4m.c | 7 +++----
hw/sparc64/niagara.c | 2 +-
hw/sparc64/sun4u.c | 2 +-
4 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index bba3aa3dee..31be3f32b0 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -139,9 +139,9 @@ static void leon3_generic_hw_init(MachineState *machine)
env->qemu_irq_ack = leon3_irq_manager;
/* Allocate RAM */
- if ((uint64_t)ram_size > (1UL << 30)) {
- error_report("Too much memory for this machine: %d, maximum 1G",
- (unsigned int)(ram_size / (1024 * 1024)));
+ if (ram_size > 1 * G_BYTE) {
+ error_report("Too much memory for this machine: %lluMB, maximum 1G",
+ ram_size / M_BYTE);
exit(1);
}
@@ -149,7 +149,7 @@ static void leon3_generic_hw_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */
- prom_size = 8 * 1024 * 1024; /* 8Mb */
+ prom_size = 8 * M_BYTE;
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom);
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 9d82490794..01b4d0c36e 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -66,7 +66,7 @@
#define KERNEL_LOAD_ADDR 0x00004000
#define CMDLINE_ADDR 0x007ff000
#define INITRD_LOAD_ADDR 0x00800000
-#define PROM_SIZE_MAX (1024 * 1024)
+#define PROM_SIZE_MAX (1 * M_BYTE)
#define PROM_VADDR 0xffd00000
#define PROM_FILENAME "openbios-sparc32"
#define CFG_ADDR 0xd00000510ULL
@@ -744,9 +744,8 @@ static void ram_init(hwaddr addr, ram_addr_t RAM_size,
/* allocate RAM */
if ((uint64_t)RAM_size > max_mem) {
- error_report("Too much memory for this machine: %d, maximum %d",
- (unsigned int)(RAM_size / (1024 * 1024)),
- (unsigned int)(max_mem / (1024 * 1024)));
+ error_report("Too much memory for this machine: %llu, maximum %llu",
+ RAM_size / M_BYTE, max_mem / M_BYTE);
exit(1);
}
dev = qdev_create(NULL, "memory");
diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c
index 1874477ef6..97a78ca9a2 100644
--- a/hw/sparc64/niagara.c
+++ b/hw/sparc64/niagara.c
@@ -84,7 +84,7 @@ typedef struct NiagaraBoardState {
#define NIAGARA_PROM_BASE 0xfff0000000ULL
#define NIAGARA_Q_OFFSET 0x10000ULL
#define NIAGARA_OBP_OFFSET 0x80000ULL
-#define PROM_SIZE_MAX (4 * 1024 * 1024)
+#define PROM_SIZE_MAX (4 * M_BYTE)
static void add_rom_or_fail(const char *file, const hwaddr addr)
{
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index b84589e0b6..7a39ec7859 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -53,7 +53,7 @@
#define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000
-#define PROM_SIZE_MAX (4 * 1024 * 1024)
+#define PROM_SIZE_MAX (4 * M_BYTE)
#define PROM_VADDR 0x000ffd00000ULL
#define PBM_SPECIAL_BASE 0x1fe00000000ULL
#define PBM_MEM_BASE 0x1ff00000000ULL
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 10/30] hw/ppc: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 09/30] hw/sparc: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 11/30] hw/s390x: " Philippe Mathieu-Daudé
` (19 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Hervé Poussineau,
Alexander Graf, David Gibson, Edgar E. Iglesias, open list:PReP
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/ppc/spapr.h | 2 +-
hw/pci-host/prep.c | 2 +-
hw/ppc/e500.c | 8 ++++----
hw/ppc/mac_oldworld.c | 7 +++----
hw/ppc/ppc405_boards.c | 8 ++++----
hw/ppc/ppc405_uc.c | 6 +++---
hw/ppc/ppc4xx_devs.c | 21 +++++++++++----------
hw/ppc/ppce500_spin.c | 2 +-
hw/ppc/prep.c | 2 +-
hw/ppc/rs6000_mc.c | 12 ++++++------
hw/ppc/virtex_ml507.c | 4 ++--
11 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 36942b378d..896eb1b0b0 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -746,7 +746,7 @@ int spapr_rng_populate_dt(void *fdt);
#define SPAPR_MAX_RAM_SLOTS 32
/* 1GB alignment for hotplug memory region */
-#define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
+#define SPAPR_HOTPLUG_MEM_ALIGN (1 * G_BYTE)
/*
* Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 01f67f9db1..d06498e131 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -70,7 +70,7 @@ typedef struct PRePPCIState {
int contiguous_map;
} PREPPCIState;
-#define BIOS_SIZE (1024 * 1024)
+#define BIOS_SIZE (1 * M_BYTE)
static inline uint32_t raven_pci_io_config(hwaddr addr)
{
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index a40d3ec3e3..02675c7be4 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -45,7 +45,7 @@
#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
#define DTC_LOAD_PAD 0x1800000
#define DTC_PAD_MASK 0xFFFFF
-#define DTB_MAX_SIZE (8 * 1024 * 1024)
+#define DTB_MAX_SIZE (8 * M_BYTE)
#define INITRD_LOAD_PAD 0x2000000
#define INITRD_PAD_MASK 0xFFFFFF
@@ -597,7 +597,7 @@ static int ppce500_prep_device_tree(MachineState *machine,
/* Create -kernel TLB entries for BookE. */
hwaddr booke206_page_size_to_tlb(uint64_t size)
{
- return 63 - clz64(size >> 10);
+ return 63 - clz64(size / K_BYTE);
}
static int booke206_initial_map_tsize(CPUPPCState *env)
@@ -913,9 +913,9 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
/* Register spinning region */
sysbus_create_simple("e500-spin", params->spin_base, NULL);
- if (cur_base < (32 * 1024 * 1024)) {
+ if (cur_base < 32 * M_BYTE) {
/* u-boot occupies memory up to 32MB, so load blobs above */
- cur_base = (32 * 1024 * 1024);
+ cur_base = 32 * M_BYTE;
}
if (params->has_mpc8xxx_gpio) {
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index c245251c5c..76bdc2c11d 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -118,10 +118,9 @@ static void ppc_heathrow_init(MachineState *machine)
}
/* allocate RAM */
- if (ram_size > (2047 << 20)) {
- fprintf(stderr,
- "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
- ((unsigned int)ram_size / (1 << 20)));
+ if (ram_size > 2047 * M_BYTE) {
+ error_report("Too much memory for this machine: %llu MB, "
+ "maximum 2047 MB", ram_size / M_BYTE);
exit(1);
}
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 0b658931ee..8c742449b8 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -41,7 +41,7 @@
#include "exec/address-spaces.h"
#define BIOS_FILENAME "ppc405_rom.bin"
-#define BIOS_SIZE (2048 * 1024)
+#define BIOS_SIZE (2 * M_BYTE)
#define KERNEL_LOAD_ADDR 0x00000000
#define INITRD_LOAD_ADDR 0x01800000
@@ -217,14 +217,14 @@ static void ref405ep_init(MachineState *machine)
memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
- ram_size = 128 * 1024 * 1024;
+ ram_size = 128 * M_BYTE;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &pic, kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
- sram_size = 512 * 1024;
+ sram_size = 512 * K_BYTE;
memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
&error_fatal);
memory_region_add_subregion(sysmem, 0xFFF00000, sram);
@@ -590,7 +590,7 @@ static void taihu_405ep_init(MachineState *machine)
bios_size = blk_getlength(blk);
/* XXX: should check that size is 32MB */
- bios_size = 32 * 1024 * 1024;
+ bios_size = 32 * M_BYTE;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 205ebcea93..0e9d5b0ff9 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -983,10 +983,10 @@ static void ppc405_ocm_init(CPUPPCState *env)
ocm = g_malloc0(sizeof(ppc405_ocm_t));
/* XXX: Size is 4096 or 0x04000000 */
- memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096,
+ memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * K_BYTE,
&error_fatal);
- memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
- 0, 4096);
+ memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
+ &ocm->isarc_ram, 0, 4 * K_BYTE);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 2e963894fe..52de988b13 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -29,6 +29,7 @@
#include "hw/boards.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
+#include "qemu/error-report.h"
#define DEBUG_UIC
@@ -353,25 +354,25 @@ static uint32_t sdram_bcr (hwaddr ram_base,
uint32_t bcr;
switch (ram_size) {
- case (4 * 1024 * 1024):
+ case 4 * M_BYTE:
bcr = 0x00000000;
break;
- case (8 * 1024 * 1024):
+ case 8 * M_BYTE:
bcr = 0x00020000;
break;
- case (16 * 1024 * 1024):
+ case 16 * M_BYTE:
bcr = 0x00040000;
break;
- case (32 * 1024 * 1024):
+ case 32 * M_BYTE:
bcr = 0x00060000;
break;
- case (64 * 1024 * 1024):
+ case 64 * M_BYTE:
bcr = 0x00080000;
break;
- case (128 * 1024 * 1024):
+ case 128 * M_BYTE:
bcr = 0x000A0000;
break;
- case (256 * 1024 * 1024):
+ case 256 * M_BYTE:
bcr = 0x000C0000;
break;
default:
@@ -399,7 +400,7 @@ static target_ulong sdram_size (uint32_t bcr)
if (sh == 7)
size = -1;
else
- size = (4 * 1024 * 1024) << sh;
+ size = (4 * M_BYTE) << sh;
return size;
}
@@ -702,8 +703,8 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
ram_size -= size_left;
if (size_left) {
- printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
- (int)(ram_size >> 20));
+ error_report("Truncating memory to %llu MiB to fit SDRAM "
+ "controller limits", ram_size / M_BYTE);
}
memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index 69ca2d0e42..b6d224c45b 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -89,7 +89,7 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
SpinInfo *curspin = data.host_ptr;
- hwaddr map_size = 64 * 1024 * 1024;
+ hwaddr map_size = 64 * M_BYTE;
hwaddr map_start;
cpu_synchronize_state(cs);
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index f7c0a48558..eae475a34d 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -59,7 +59,7 @@
#define CFG_ADDR 0xf0000510
-#define BIOS_SIZE (1024 * 1024)
+#define BIOS_SIZE (1 * M_BYTE)
#define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c
index b6135650bd..6999994fe4 100644
--- a/hw/ppc/rs6000_mc.c
+++ b/hw/ppc/rs6000_mc.c
@@ -109,7 +109,7 @@ static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
size = end_address - start_address;
memory_region_set_enabled(&s->simm[socket - 1], size != 0);
memory_region_set_address(&s->simm[socket - 1],
- start_address * 8 * 1024 * 1024);
+ start_address * 8 * M_BYTE);
}
}
}
@@ -140,7 +140,7 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
{
RS6000MCState *s = RS6000MC_DEVICE(dev);
int socket = 0;
- unsigned int ram_size = s->ram_size / (1024 * 1024);
+ unsigned int ram_size = s->ram_size / M_BYTE;
while (socket < 6) {
if (ram_size >= 64) {
@@ -163,8 +163,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
char name[] = "simm.?";
name[5] = socket + '0';
memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
- name, s->simm_size[socket]
- * 1024 * 1024);
+ name,
+ s->simm_size[socket] * M_BYTE);
memory_region_add_subregion_overlap(get_system_memory(), 0,
&s->simm[socket], socket);
}
@@ -172,8 +172,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **errp)
if (ram_size) {
/* unable to push all requested RAM in SIMMs */
error_setg(errp, "RAM size incompatible with this board. "
- "Try again with something else, like %d MB",
- s->ram_size / 1024 / 1024 - ram_size);
+ "Try again with something else, like %lld MB",
+ s->ram_size / M_BYTE - ram_size);
return;
}
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 77a1778e07..dcfb6c2670 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -47,7 +47,7 @@
#include "sysemu/block-backend.h"
#define EPAPR_MAGIC (0x45504150)
-#define FLASH_SIZE (16 * 1024 * 1024)
+#define FLASH_SIZE (16 * M_BYTE)
#define INTC_BASEADDR 0x81800000
#define UART16550_BASEADDR 0x83e01003
@@ -237,7 +237,7 @@ static void virtex_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- (64 * 1024), FLASH_SIZE >> 16,
+ 64 * K_BYTE, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 11/30] hw/s390x: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 10/30] hw/ppc: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 12/30] hw/hppa: " Philippe Mathieu-Daudé
` (18 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Cornelia Huck,
Richard Henderson, Alexander Graf, David Hildenbrand,
Christian Borntraeger, open list:S390
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
---
hw/s390x/sclp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
index 047d577313..2ffec8f675 100644
--- a/hw/s390x/sclp.c
+++ b/hw/s390x/sclp.c
@@ -288,8 +288,8 @@ static void sclp_realize(DeviceState *dev, Error **errp)
ret = s390_set_memory_limit(machine->maxram_size, &hw_limit);
if (ret == -E2BIG) {
- error_setg(&err, "host supports a maximum of %" PRIu64 " GB",
- hw_limit >> 30);
+ error_setg(&err, "host supports a maximum of %llu GB",
+ hw_limit / G_BYTE);
} else if (ret) {
error_setg(&err, "setting the guest size failed");
}
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 12/30] hw/hppa: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 11/30] hw/s390x: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 13/30] hw/xtensa: " Philippe Mathieu-Daudé
` (17 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Richard Henderson
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/hppa/dino.c | 2 +-
hw/hppa/machine.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index 15aefde09c..7728123cc8 100644
--- a/hw/hppa/dino.c
+++ b/hw/hppa/dino.c
@@ -76,7 +76,7 @@
/* #define xxx 0x200 - bit 9 not used */
#define RS232INT 0x400
-#define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */
+#define DINO_MEM_CHUNK_SIZE (8 * M_BYTE)
#define DINO_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 22a15112df..8fd364ad43 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -177,8 +177,8 @@ static void machine_hppa_init(MachineState *machine)
}
qemu_log_mask(CPU_LOG_PAGE, "Kernel loaded at 0x%08" PRIx64
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64
- ", size %ld kB.\n",
- kernel_low, kernel_high, kernel_entry, size / 1024);
+ ", size %llu kB\n",
+ kernel_low, kernel_high, kernel_entry, size / K_BYTE);
if (kernel_cmdline) {
cpu[0]->env.gr[24] = 0x4000;
@@ -202,8 +202,8 @@ static void machine_hppa_init(MachineState *machine)
(1) Due to sign-extension problems and PDC,
put the initrd no higher than 1G.
(2) Reserve 64k for stack. */
- initrd_base = MIN(ram_size, 1024 * 1024 * 1024);
- initrd_base = initrd_base - 64 * 1024;
+ initrd_base = MIN(ram_size, 1 * G_BYTE);
+ initrd_base = initrd_base - 64 * K_BYTE;
initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK;
if (initrd_base < kernel_high) {
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 13/30] hw/xtensa: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 12/30] hw/hppa: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 14/30] hw/alpha: " Philippe Mathieu-Daudé
` (16 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Max Filippov
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
---
hw/xtensa/xtfpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 70686a2eb1..922417af15 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -230,7 +230,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
- const unsigned system_io_size = 224 * 1024 * 1024;
+ const unsigned system_io_size = 224 * M_BYTE;
int n;
for (n = 0; n < smp_cpus; n++) {
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 14/30] hw/alpha: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 13/30] hw/xtensa: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 15/30] hw/lm32: " Philippe Mathieu-Daudé
` (15 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Richard Henderson
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/alpha/typhoon.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 6a40869488..0acfb4b1d0 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -812,8 +812,6 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq,
AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
{
- const uint64_t MB = 1024 * 1024;
- const uint64_t GB = 1024 * MB;
MemoryRegion *addr_space = get_system_memory();
DeviceState *dev;
TyphoonState *s;
@@ -854,30 +852,30 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",
- 256*MB);
+ 256 * M_BYTE);
memory_region_add_subregion(addr_space, 0x80180000000ULL,
&s->pchip.region);
/* Cchip CSRs, 0x801.A000.0000, 256MB. */
memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",
- 256*MB);
+ 256 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801a0000000ULL,
&s->cchip.region);
/* Dchip CSRs, 0x801.B000.0000, 256MB. */
memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",
- 256*MB);
+ 256 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801b0000000ULL,
&s->dchip_region);
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
- memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB);
+ memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4 * G_BYTE);
memory_region_add_subregion(addr_space, 0x80000000000ULL,
&s->pchip.reg_mem);
/* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_ignore_ops,
- NULL, "pci0-io", 32*MB);
+ NULL, "pci0-io", 32 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io);
@@ -898,13 +896,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops,
- b, "pci0-iack", 64*MB);
+ b, "pci0-iack", 64 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801f8000000ULL,
&s->pchip.reg_iack);
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops,
- b, "pci0-conf", 16*MB);
+ b, "pci0-conf", 16 * M_BYTE);
memory_region_add_subregion(addr_space, 0x801fe000000ULL,
&s->pchip.reg_conf);
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 15/30] hw/lm32: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 14/30] hw/alpha: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 16/30] hw/sh4: " Philippe Mathieu-Daudé
` (14 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Michael Walle
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/lm32/lm32_boards.c | 12 ++++++------
hw/lm32/milkymist.c | 8 ++++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c
index 527bcc229c..15315101be 100644
--- a/hw/lm32/lm32_boards.c
+++ b/hw/lm32/lm32_boards.c
@@ -88,10 +88,10 @@ static void lm32_evr_init(MachineState *machine)
/* memory map */
hwaddr flash_base = 0x04000000;
- size_t flash_sector_size = 256 * 1024;
- size_t flash_size = 32 * 1024 * 1024;
+ size_t flash_sector_size = 256 * K_BYTE;
+ size_t flash_size = 32 * M_BYTE;
hwaddr ram_base = 0x08000000;
- size_t ram_size = 64 * 1024 * 1024;
+ size_t ram_size = 64 * M_BYTE;
hwaddr timer0_base = 0x80002000;
hwaddr uart0_base = 0x80006000;
hwaddr timer1_base = 0x8000a000;
@@ -174,10 +174,10 @@ static void lm32_uclinux_init(MachineState *machine)
/* memory map */
hwaddr flash_base = 0x04000000;
- size_t flash_sector_size = 256 * 1024;
- size_t flash_size = 32 * 1024 * 1024;
+ size_t flash_sector_size = 256 * K_BYTE;
+ size_t flash_size = 32 * M_BYTE;
hwaddr ram_base = 0x08000000;
- size_t ram_size = 64 * 1024 * 1024;
+ size_t ram_size = 64 * M_BYTE;
hwaddr uart0_base = 0x80000000;
hwaddr timer0_base = 0x80002000;
hwaddr timer1_base = 0x80010000;
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index c28379399f..b884b825bc 100644
--- a/hw/lm32/milkymist.c
+++ b/hw/lm32/milkymist.c
@@ -36,7 +36,7 @@
#define BIOS_FILENAME "mmone-bios.bin"
#define BIOS_OFFSET 0x00860000
-#define BIOS_SIZE (512*1024)
+#define BIOS_SIZE (512 * K_BYTE)
#define KERNEL_LOAD_ADDR 0x40000000
typedef struct {
@@ -95,10 +95,10 @@ milkymist_init(MachineState *machine)
/* memory map */
hwaddr flash_base = 0x00000000;
- size_t flash_sector_size = 128 * 1024;
- size_t flash_size = 32 * 1024 * 1024;
+ size_t flash_sector_size = 128 * K_BYTE;
+ size_t flash_size = 32 * M_BYTE;
hwaddr sdram_base = 0x40000000;
- size_t sdram_size = 128 * 1024 * 1024;
+ size_t sdram_size = 128 * M_BYTE;
hwaddr initrd_base = sdram_base + 0x1002000;
hwaddr cmdline_base = sdram_base + 0x1000000;
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 16/30] hw/sh4: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 15/30] hw/lm32: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 17/30] hw/tricore: " Philippe Mathieu-Daudé
` (13 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Kevin Wolf, Max Reitz,
Magnus Damm, Aurelien Jarno, open list:Block layer core
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/block/tc58128.c | 2 +-
hw/sh4/r2d.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
index 1d9f7ee000..3e658d509f 100644
--- a/hw/block/tc58128.c
+++ b/hw/block/tc58128.c
@@ -26,7 +26,7 @@ typedef struct {
static tc58128_dev tc58128_devs[2];
-#define FLASH_SIZE (16*1024*1024)
+#define FLASH_SIZE (16 * M_BYTE)
static void init_dev(tc58128_dev * dev, const char *filename)
{
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 458ed83297..720bd6ad04 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -292,7 +292,7 @@ static void r2d_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- (16 * 1024), FLASH_SIZE >> 16,
+ 16 * K_BYTE, FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
0x555, 0x2aa, 0);
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 17/30] hw/tricore: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 16/30] hw/sh4: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 18/30] hw/microblaze: " Philippe Mathieu-Daudé
` (12 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Bastian Koppelmann
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
hw/tricore/tricore_testboard.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c
index ac75eb2128..032bcc8efb 100644
--- a/hw/tricore/tricore_testboard.c
+++ b/hw/tricore/tricore_testboard.c
@@ -74,17 +74,17 @@ static void tricore_testboard_init(MachineState *machine, int board_id)
cpu = TRICORE_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram",
- 2 * 1024 * 1024, &error_fatal);
+ 2 * M_BYTE, &error_fatal);
memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram",
- 4 * 1024 * 1024, &error_fatal);
- memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48 * 1024,
+ 4 * M_BYTE, &error_fatal);
+ memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48 * K_BYTE,
&error_fatal);
- memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48 * 1024,
+ memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48 * K_BYTE,
&error_fatal);
memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram",
- 16 * 1024, &error_fatal);
+ 16 * K_BYTE, &error_fatal);
memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram",
- 32 * 1024, &error_fatal);
+ 32 * K_BYTE, &error_fatal);
memory_region_add_subregion(sysmem, 0x80000000, ext_cram);
memory_region_add_subregion(sysmem, 0xa1000000, ext_dram);
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 18/30] hw/microblaze: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 17/30] hw/tricore: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 19/30] hw/nios2: " Philippe Mathieu-Daudé
` (11 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Edgar E. Iglesias
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/microblaze/petalogix_ml605_mmu.c | 6 +++---
hw/microblaze/petalogix_s3adsp1800_mmu.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index b664dc0f9c..d2b316fcba 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -45,8 +45,8 @@
#include "hw/stream.h"
-#define LMB_BRAM_SIZE (128 * 1024)
-#define FLASH_SIZE (32 * 1024 * 1024)
+#define LMB_BRAM_SIZE (128 * K_BYTE)
+#define FLASH_SIZE (32 * M_BYTE)
#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
@@ -110,7 +110,7 @@ petalogix_ml605_init(MachineState *machine)
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- (64 * 1024), FLASH_SIZE >> 16,
+ 64 * K_BYTE, FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0);
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index 5cb4deb69e..d93f7184a5 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -40,8 +40,8 @@
#include "boot.h"
-#define LMB_BRAM_SIZE (128 * 1024)
-#define FLASH_SIZE (16 * 1024 * 1024)
+#define LMB_BRAM_SIZE (128 * K_BYTE)
+#define FLASH_SIZE (16 * M_BYTE)
#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
@@ -88,7 +88,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- (64 * 1024), FLASH_SIZE >> 16,
+ 64 * K_BYTE, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);
dev = qdev_create(NULL, "xlnx.xps-intc");
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 19/30] hw/nios2: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 18/30] hw/microblaze: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 20/30] hw/cris: " Philippe Mathieu-Daudé
` (10 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Chris Wulff, Marek Vasut
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/nios2/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c
index 771e00267b..911f28c0d8 100644
--- a/hw/nios2/boot.c
+++ b/hw/nios2/boot.c
@@ -176,7 +176,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
high = ddr_base + kernel_size;
}
- high = ROUND_UP(high, 1024 * 1024);
+ high = ROUND_UP(high, 1 * M_BYTE);
/* If initrd is available, it goes after the kernel, aligned to 1M. */
if (initrd_filename) {
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 20/30] hw/cris: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 19/30] hw/nios2: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 21/30] hw/misc: " Philippe Mathieu-Daudé
` (9 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Edgar E. Iglesias
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/cris/axis_dev88.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c
index 9ccc4350a5..1dea3c594c 100644
--- a/hw/cris/axis_dev88.c
+++ b/hw/cris/axis_dev88.c
@@ -243,7 +243,7 @@ static const MemoryRegionOps gpio_ops = {
},
};
-#define INTMEM_SIZE (128 * 1024)
+#define INTMEM_SIZE (128 * K_BYTE)
static struct cris_load_info li;
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 21/30] hw/misc: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 20/30] hw/cris: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 19:02 ` Jiri Slaby
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 23/30] hw/net: " Philippe Mathieu-Daudé
` (8 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Jiri Slaby
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/misc/auxbus.c | 2 +-
hw/misc/edu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
index b4cacd664b..c78aaebcbe 100644
--- a/hw/misc/auxbus.c
+++ b/hw/misc/auxbus.c
@@ -68,7 +68,7 @@ AUXBus *aux_init_bus(DeviceState *parent, const char *name)
/* Memory related. */
bus->aux_io = g_malloc(sizeof(*bus->aux_io));
- memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
+ memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 2 * M_BYTE);
address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
return bus;
}
diff --git a/hw/misc/edu.c b/hw/misc/edu.c
index 34eb05d213..ce8235dfc4 100644
--- a/hw/misc/edu.c
+++ b/hw/misc/edu.c
@@ -357,7 +357,7 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp)
edu, QEMU_THREAD_JOINABLE);
memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
- "edu-mmio", 1 << 20);
+ "edu-mmio", 1 * M_BYTE);
pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
}
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v2 21/30] hw/misc: use the BYTE-based definitions
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 21/30] hw/misc: " Philippe Mathieu-Daudé
@ 2018-03-05 19:02 ` Jiri Slaby
2018-03-05 19:05 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 40+ messages in thread
From: Jiri Slaby @ 2018-03-05 19:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-trivial; +Cc: qemu-devel
On 03/05/2018, 12:27 PM, Philippe Mathieu-Daudé wrote:
> --- a/hw/misc/auxbus.c
> +++ b/hw/misc/auxbus.c
> @@ -68,7 +68,7 @@ AUXBus *aux_init_bus(DeviceState *parent, const char *name)
>
> /* Memory related. */
> bus->aux_io = g_malloc(sizeof(*bus->aux_io));
> - memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
> + memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 2 * M_BYTE);
Only M_BYTE, not "2 *".
> address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
> return bus;
> }
> diff --git a/hw/misc/edu.c b/hw/misc/edu.c
> index 34eb05d213..ce8235dfc4 100644
> --- a/hw/misc/edu.c
> +++ b/hw/misc/edu.c
> @@ -357,7 +357,7 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp)
> edu, QEMU_THREAD_JOINABLE);
>
> memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
> - "edu-mmio", 1 << 20);
> + "edu-mmio", 1 * M_BYTE);
"1 * " is superfluous
thanks,
--
js
suse labs
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/30] hw/misc: use the BYTE-based definitions
2018-03-05 19:02 ` Jiri Slaby
@ 2018-03-05 19:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 19:05 UTC (permalink / raw)
To: Jiri Slaby, qemu-trivial; +Cc: qemu-devel
Hi Jiri,
On 03/05/2018 04:02 PM, Jiri Slaby wrote:
> On 03/05/2018, 12:27 PM, Philippe Mathieu-Daudé wrote:
>> --- a/hw/misc/auxbus.c
>> +++ b/hw/misc/auxbus.c
>> @@ -68,7 +68,7 @@ AUXBus *aux_init_bus(DeviceState *parent, const char *name)
>>
>> /* Memory related. */
>> bus->aux_io = g_malloc(sizeof(*bus->aux_io));
>> - memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
>> + memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 2 * M_BYTE);
>
> Only M_BYTE, not "2 *".
Yes! I totally missed this :/
>
>> address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
>> return bus;
>> }
>> diff --git a/hw/misc/edu.c b/hw/misc/edu.c
>> index 34eb05d213..ce8235dfc4 100644
>> --- a/hw/misc/edu.c
>> +++ b/hw/misc/edu.c
>> @@ -357,7 +357,7 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp)
>> edu, QEMU_THREAD_JOINABLE);
>>
>> memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
>> - "edu-mmio", 1 << 20);
>> + "edu-mmio", 1 * M_BYTE);
>
> "1 * " is superfluous
I kept "1 * " to be consistent with the other uses, I find it easier to
review (or modify).
Thanks for your review!
Phil.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v2 23/30] hw/net: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 21/30] hw/misc: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 24/30] hw/ipack: " Philippe Mathieu-Daudé
` (7 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Dmitry Fleytman,
Jason Wang, Stefan Weil, Beniamino Galvani,
open list:Allwinner-a10
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/net/allwinner_emac.h | 4 ++--
hw/net/e1000e.c | 6 +++---
hw/net/eepro100.c | 6 ++----
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/include/hw/net/allwinner_emac.h b/include/hw/net/allwinner_emac.h
index 4cc8aab7ec..93ec0e7067 100644
--- a/include/hw/net/allwinner_emac.h
+++ b/include/hw/net/allwinner_emac.h
@@ -125,8 +125,8 @@
#define EMAC_INT_RX (1 << 8)
/* Due to lack of specifications, size of fifos is chosen arbitrarily */
-#define TX_FIFO_SIZE (4 * 1024)
-#define RX_FIFO_SIZE (32 * 1024)
+#define TX_FIFO_SIZE (4 * K_BYTE)
+#define RX_FIFO_SIZE (32 * K_BYTE)
#define NUM_TX_FIFOS 2
#define RX_HDR_SIZE 8
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
index 16a9417a85..767b35fca8 100644
--- a/hw/net/e1000e.c
+++ b/hw/net/e1000e.c
@@ -81,10 +81,10 @@ typedef struct E1000EState {
#define E1000E_IO_IDX 2
#define E1000E_MSIX_IDX 3
-#define E1000E_MMIO_SIZE (128 * 1024)
-#define E1000E_FLASH_SIZE (128 * 1024)
+#define E1000E_MMIO_SIZE (128 * K_BYTE)
+#define E1000E_FLASH_SIZE (128 * K_BYTE)
#define E1000E_IO_SIZE (32)
-#define E1000E_MSIX_SIZE (16 * 1024)
+#define E1000E_MSIX_SIZE (16 * K_BYTE)
#define E1000E_MSIX_TABLE (0x0000)
#define E1000E_MSIX_PBA (0x2000)
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index a07a63247e..6fdeb05259 100644
--- a/hw/net/eepro100.c
+++ b/hw/net/eepro100.c
@@ -60,8 +60,6 @@
* changed to pad short packets itself. */
#define CONFIG_PAD_RECEIVED_FRAMES
-#define KiB 1024
-
/* Debug EEPRO100 card. */
#if 0
# define DEBUG_EEPRO100
@@ -104,9 +102,9 @@
/* Use 64 word EEPROM. TODO: could be a runtime option. */
#define EEPROM_SIZE 64
-#define PCI_MEM_SIZE (4 * KiB)
+#define PCI_MEM_SIZE (4 * K_BYTE)
#define PCI_IO_SIZE 64
-#define PCI_FLASH_SIZE (128 * KiB)
+#define PCI_FLASH_SIZE (128 * K_BYTE)
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 24/30] hw/ipack: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 23/30] hw/net: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 25/30] hw/scsi: " Philippe Mathieu-Daudé
` (6 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Alberto Garcia
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alberto Garcia <berto@igalia.com>
---
hw/ipack/tpci200.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c
index da05c8589d..56c0ad8932 100644
--- a/hw/ipack/tpci200.c
+++ b/hw/ipack/tpci200.c
@@ -597,9 +597,9 @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
memory_region_init_io(&s->las1, OBJECT(s), &tpci200_las1_ops,
s, "tpci200_las1", 1024);
memory_region_init_io(&s->las2, OBJECT(s), &tpci200_las2_ops,
- s, "tpci200_las2", 1024*1024*32);
+ s, "tpci200_las2", 32 * M_BYTE);
memory_region_init_io(&s->las3, OBJECT(s), &tpci200_las3_ops,
- s, "tpci200_las3", 1024*1024*16);
+ s, "tpci200_las3", 16 * M_BYTE);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las0);
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 25/30] hw/scsi: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 24/30] hw/ipack: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 26/30] hw/smbios: " Philippe Mathieu-Daudé
` (5 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Paolo Bonzini, Fam Zheng
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/scsi/scsi-disk.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index 49d2559d93..bfdb34a71c 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -44,13 +44,13 @@ do { printf("scsi-disk: " fmt , ## __VA_ARGS__); } while (0)
#include <scsi/sg.h>
#endif
-#define SCSI_WRITE_SAME_MAX 524288
-#define SCSI_DMA_BUF_SIZE 131072
+#define SCSI_WRITE_SAME_MAX (512 * K_BYTE)
+#define SCSI_DMA_BUF_SIZE (128 * K_BYTE)
#define SCSI_MAX_INQUIRY_LEN 256
#define SCSI_MAX_MODE_LEN 256
-#define DEFAULT_DISCARD_GRANULARITY 4096
-#define DEFAULT_MAX_UNMAP_SIZE (1 << 30) /* 1 GB */
+#define DEFAULT_DISCARD_GRANULARITY (4 * K_BYTE)
+#define DEFAULT_MAX_UNMAP_SIZE (1 * G_BYTE)
#define DEFAULT_MAX_IO_SIZE INT_MAX /* 2 GB - 1 block */
#define TYPE_SCSI_DISK_BASE "scsi-disk-base"
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 26/30] hw/smbios: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (23 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 25/30] hw/scsi: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-06 9:02 ` Igor Mammedov
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 27/30] vfio/pci: " Philippe Mathieu-Daudé
` (4 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Michael S. Tsirkin,
Igor Mammedov
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/smbios/smbios.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index 27a07e96f4..fa02f9ce3f 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -625,10 +625,6 @@ static void smbios_build_type_11_table(void)
SMBIOS_BUILD_TABLE_POST;
}
-#define ONE_KB ((ram_addr_t)1 << 10)
-#define ONE_MB ((ram_addr_t)1 << 20)
-#define ONE_GB ((ram_addr_t)1 << 30)
-
#define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */
static void smbios_build_type_16_table(unsigned dimm_cnt)
@@ -640,7 +636,7 @@ static void smbios_build_type_16_table(unsigned dimm_cnt)
t->location = 0x01; /* Other */
t->use = 0x03; /* System memory */
t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */
- size_kb = QEMU_ALIGN_UP(ram_size, ONE_KB) / ONE_KB;
+ size_kb = QEMU_ALIGN_UP(ram_size, K_BYTE) / K_BYTE;
if (size_kb < MAX_T16_STD_SZ) {
t->maximum_capacity = cpu_to_le32(size_kb);
t->extended_maximum_capacity = cpu_to_le64(0);
@@ -668,7 +664,7 @@ static void smbios_build_type_17_table(unsigned instance, uint64_t size)
t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
t->total_width = cpu_to_le16(0xFFFF); /* Unknown */
t->data_width = cpu_to_le16(0xFFFF); /* Unknown */
- size_mb = QEMU_ALIGN_UP(size, ONE_MB) / ONE_MB;
+ size_mb = QEMU_ALIGN_UP(size, M_BYTE) / M_BYTE;
if (size_mb < MAX_T17_STD_SZ) {
t->size = cpu_to_le16(size_mb);
t->extended_size = cpu_to_le32(0);
@@ -707,8 +703,8 @@ static void smbios_build_type_19_table(unsigned instance,
end = start + size - 1;
assert(end > start);
- start_kb = start / ONE_KB;
- end_kb = end / ONE_KB;
+ start_kb = start / K_BYTE;
+ end_kb = end / K_BYTE;
if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) {
t->starting_address = cpu_to_le32(start_kb);
t->ending_address = cpu_to_le32(end_kb);
@@ -869,7 +865,7 @@ void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
smbios_build_type_11_table();
-#define MAX_DIMM_SZ (16ll * ONE_GB)
+#define MAX_DIMM_SZ (16 * G_BYTE)
#define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \
: ((ram_size - 1) % MAX_DIMM_SZ) + 1)
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v2 26/30] hw/smbios: use the BYTE-based definitions
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 26/30] hw/smbios: " Philippe Mathieu-Daudé
@ 2018-03-06 9:02 ` Igor Mammedov
0 siblings, 0 replies; 40+ messages in thread
From: Igor Mammedov @ 2018-03-06 9:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-trivial, Michael S. Tsirkin, qemu-devel
On Mon, 5 Mar 2018 08:27:28 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> It eases code review, unit is explicit.
>
> Patch generated using:
>
> $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
>
> and modified manually.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/smbios/smbios.c | 14 +++++---------
> 1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
> index 27a07e96f4..fa02f9ce3f 100644
> --- a/hw/smbios/smbios.c
> +++ b/hw/smbios/smbios.c
> @@ -625,10 +625,6 @@ static void smbios_build_type_11_table(void)
> SMBIOS_BUILD_TABLE_POST;
> }
>
> -#define ONE_KB ((ram_addr_t)1 << 10)
> -#define ONE_MB ((ram_addr_t)1 << 20)
> -#define ONE_GB ((ram_addr_t)1 << 30)
> -
> #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */
>
> static void smbios_build_type_16_table(unsigned dimm_cnt)
> @@ -640,7 +636,7 @@ static void smbios_build_type_16_table(unsigned dimm_cnt)
> t->location = 0x01; /* Other */
> t->use = 0x03; /* System memory */
> t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */
> - size_kb = QEMU_ALIGN_UP(ram_size, ONE_KB) / ONE_KB;
> + size_kb = QEMU_ALIGN_UP(ram_size, K_BYTE) / K_BYTE;
> if (size_kb < MAX_T16_STD_SZ) {
> t->maximum_capacity = cpu_to_le32(size_kb);
> t->extended_maximum_capacity = cpu_to_le64(0);
> @@ -668,7 +664,7 @@ static void smbios_build_type_17_table(unsigned instance, uint64_t size)
> t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
> t->total_width = cpu_to_le16(0xFFFF); /* Unknown */
> t->data_width = cpu_to_le16(0xFFFF); /* Unknown */
> - size_mb = QEMU_ALIGN_UP(size, ONE_MB) / ONE_MB;
> + size_mb = QEMU_ALIGN_UP(size, M_BYTE) / M_BYTE;
> if (size_mb < MAX_T17_STD_SZ) {
> t->size = cpu_to_le16(size_mb);
> t->extended_size = cpu_to_le32(0);
> @@ -707,8 +703,8 @@ static void smbios_build_type_19_table(unsigned instance,
>
> end = start + size - 1;
> assert(end > start);
> - start_kb = start / ONE_KB;
> - end_kb = end / ONE_KB;
> + start_kb = start / K_BYTE;
> + end_kb = end / K_BYTE;
> if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) {
> t->starting_address = cpu_to_le32(start_kb);
> t->ending_address = cpu_to_le32(end_kb);
> @@ -869,7 +865,7 @@ void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
>
> smbios_build_type_11_table();
>
> -#define MAX_DIMM_SZ (16ll * ONE_GB)
> +#define MAX_DIMM_SZ (16 * G_BYTE)
> #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \
> : ((ram_size - 1) % MAX_DIMM_SZ) + 1)
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Qemu-devel] [PATCH v2 27/30] vfio/pci: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (24 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 26/30] hw/smbios: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 28/30] ivshmem: " Philippe Mathieu-Daudé
` (3 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel, Alex Williamson
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/vfio/pci-quirks.c | 8 ++++----
hw/vfio/pci.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index e5779a7ad3..3c091106dd 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1255,9 +1255,9 @@ static int vfio_igd_gtt_max(VFIOPCIDevice *vdev)
ggms = 1 << ggms;
}
- ggms *= 1024 * 1024;
+ ggms *= M_BYTE;
- return (ggms / (4 * 1024)) * (gen < 8 ? 4 : 8);
+ return (ggms / (4 * K_BYTE)) * (gen < 8 ? 4 : 8);
}
/*
@@ -1514,7 +1514,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr)
igd->vdev = vdev;
igd->index = ~0;
igd->bdsm = vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4);
- igd->bdsm &= ~((1 << 20) - 1); /* 1MB aligned */
+ igd->bdsm &= ~((1 * M_BYTE) - 1); /* 1MB aligned */
memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_quirk,
igd, "vfio-igd-index-quirk", 4);
@@ -1561,7 +1561,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr)
* config offset 0x5C.
*/
bdsm_size = g_malloc(sizeof(*bdsm_size));
- *bdsm_size = cpu_to_le64((ggms_mb + gms_mb) * 1024 * 1024);
+ *bdsm_size = cpu_to_le64((ggms_mb + gms_mb) * M_BYTE);
fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size",
bdsm_size, sizeof(*bdsm_size));
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 033cc8dea1..db337476ef 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1408,7 +1408,7 @@ static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp)
}
/* 2GB max size for 32-bit BARs, cannot double if already > 1G */
- if (vdev->bars[target_bar].size > (1 * 1024 * 1024 * 1024) &&
+ if (vdev->bars[target_bar].size > 1 * G_BYTE &&
!vdev->bars[target_bar].mem64) {
error_setg(errp, "Invalid MSI-X relocation BAR %d, "
"no space to extend 32-bit BAR", target_bar);
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 28/30] ivshmem: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (25 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 27/30] vfio/pci: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 29/30] tpm: " Philippe Mathieu-Daudé
` (2 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial; +Cc: Philippe Mathieu-Daudé, qemu-devel
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
hw/misc/ivshmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 16f03701b7..9b3ad96471 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -1302,7 +1302,7 @@ static void ivshmem_realize(PCIDevice *dev, Error **errp)
}
if (s->sizearg == NULL) {
- s->legacy_size = 4 << 20; /* 4 MB default */
+ s->legacy_size = 4 * M_BYTE; /* 4 MB default */
} else {
int ret;
uint64_t size;
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 29/30] tpm: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (26 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 28/30] ivshmem: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 30/30] xen: " Philippe Mathieu-Daudé
[not found] ` <20180305112732.26471-23-f4bug@amsat.org>
29 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Stefan Berger,
Michael S. Tsirkin, Igor Mammedov
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
include/hw/acpi/tpm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h
index 46ac4dc581..c01e3441f5 100644
--- a/include/hw/acpi/tpm.h
+++ b/include/hw/acpi/tpm.h
@@ -176,7 +176,7 @@ REG32(CRB_DATA_BUFFER, 0x80)
#define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
#define TPM_CRB_R_MAX R_CRB_DATA_BUFFER
-#define TPM_LOG_AREA_MINIMUM_SIZE (64 * 1024)
+#define TPM_LOG_AREA_MINIMUM_SIZE (64 * K_BYTE)
#define TPM_TCPA_ACPI_CLASS_CLIENT 0
#define TPM_TCPA_ACPI_CLASS_SERVER 1
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Qemu-devel] [PATCH v2 30/30] xen: use the BYTE-based definitions
2018-03-05 11:27 [Qemu-devel] [PATCH v2 00/30] hw: use the BYTE-based definitions when useful Philippe Mathieu-Daudé
` (27 preceding siblings ...)
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 29/30] tpm: " Philippe Mathieu-Daudé
@ 2018-03-05 11:27 ` Philippe Mathieu-Daudé
2018-03-05 18:53 ` Anthony PERARD
[not found] ` <20180305112732.26471-23-f4bug@amsat.org>
29 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-05 11:27 UTC (permalink / raw)
To: qemu-trivial
Cc: Philippe Mathieu-Daudé, qemu-devel, Stefano Stabellini,
Anthony Perard, Kevin Wolf, Max Reitz, open list:X86,
open list:Block layer core
It eases code review, unit is explicit.
Patch generated using:
$ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
and modified manually.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alan Robinson <Alan.Robinson@ts.fujitsu.com>
---
hw/block/xen_disk.c | 4 ++--
hw/xenpv/xen_domainbuild.c | 10 +++++-----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/block/xen_disk.c b/hw/block/xen_disk.c
index f74fcd42d1..557005b5e5 100644
--- a/hw/block/xen_disk.c
+++ b/hw/block/xen_disk.c
@@ -1153,9 +1153,9 @@ static int blk_connect(struct XenDevice *xendev)
}
xen_pv_printf(xendev, 1, "type \"%s\", fileproto \"%s\", filename \"%s\","
- " size %" PRId64 " (%" PRId64 " MB)\n",
+ " size %" PRId64 " (%llu MB)\n",
blkdev->type, blkdev->fileproto, blkdev->filename,
- blkdev->file_size, blkdev->file_size >> 20);
+ blkdev->file_size, blkdev->file_size / M_BYTE);
/* Fill in number of sector size and number of sectors */
xenstore_write_be_int(&blkdev->xendev, "sector-size", blkdev->file_blk);
diff --git a/hw/xenpv/xen_domainbuild.c b/hw/xenpv/xen_domainbuild.c
index 027f76fad1..7c8bde20cd 100644
--- a/hw/xenpv/xen_domainbuild.c
+++ b/hw/xenpv/xen_domainbuild.c
@@ -75,9 +75,9 @@ int xenstore_domain_init1(const char *kernel, const char *ramdisk,
xenstore_write_str(dom, "vm", vm);
/* memory */
- xenstore_write_int(dom, "memory/target", ram_size >> 10); // kB
- xenstore_write_int(vm, "memory", ram_size >> 20); // MB
- xenstore_write_int(vm, "maxmem", ram_size >> 20); // MB
+ xenstore_write_int(dom, "memory/target", ram_size / K_BYTE);
+ xenstore_write_int(vm, "memory", ram_size / M_BYTE);
+ xenstore_write_int(vm, "maxmem", ram_size / M_BYTE);
/* cpus */
for (i = 0; i < smp_cpus; i++) {
@@ -260,7 +260,7 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
}
#endif
- rc = xc_domain_setmaxmem(xen_xc, xen_domid, ram_size >> 10);
+ rc = xc_domain_setmaxmem(xen_xc, xen_domid, ram_size / K_BYTE);
if (rc < 0) {
fprintf(stderr, "xen: xc_domain_setmaxmem() failed\n");
goto err;
@@ -269,7 +269,7 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
xenstore_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0);
console_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0);
- rc = xc_linux_build(xen_xc, xen_domid, ram_size >> 20,
+ rc = xc_linux_build(xen_xc, xen_domid, ram_size / M_BYTE,
kernel, ramdisk, cmdline,
0, flags,
xenstore_port, &xenstore_mfn,
--
2.16.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Qemu-devel] [PATCH v2 30/30] xen: use the BYTE-based definitions
2018-03-05 11:27 ` [Qemu-devel] [PATCH v2 30/30] xen: " Philippe Mathieu-Daudé
@ 2018-03-05 18:53 ` Anthony PERARD
0 siblings, 0 replies; 40+ messages in thread
From: Anthony PERARD @ 2018-03-05 18:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-trivial, qemu-devel, Stefano Stabellini, Kevin Wolf,
Max Reitz, open list:X86, open list:Block layer core
On Mon, Mar 05, 2018 at 08:27:32AM -0300, Philippe Mathieu-Daudé wrote:
> It eases code review, unit is explicit.
>
> Patch generated using:
>
> $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
>
> and modified manually.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Alan Robinson <Alan.Robinson@ts.fujitsu.com>
> ---
> hw/block/xen_disk.c | 4 ++--
> hw/xenpv/xen_domainbuild.c | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Thanks,
--
Anthony PERARD
^ permalink raw reply [flat|nested] 40+ messages in thread
[parent not found: <20180305112732.26471-23-f4bug@amsat.org>]
* Re: [Qemu-devel] [PATCH v2 22/30] hw/display: use the BYTE-based definitions
[not found] ` <20180305112732.26471-23-f4bug@amsat.org>
@ 2018-03-05 18:52 ` Anthony PERARD
0 siblings, 0 replies; 40+ messages in thread
From: Anthony PERARD @ 2018-03-05 18:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-trivial, qemu-devel, Gerd Hoffmann, Michael S. Tsirkin,
Stefano Stabellini, open list:X86
On Mon, Mar 05, 2018 at 08:27:24AM -0300, Philippe Mathieu-Daudé wrote:
> It eases code review, unit is explicit.
>
> Patch generated using:
>
> $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
>
> and modified manually.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
> hw/display/xenfb.c | 2 +-
> diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c
> index f5afcc0358..1ae660519a 100644
> --- a/hw/display/xenfb.c
> +++ b/hw/display/xenfb.c
> @@ -889,7 +889,7 @@ static int fb_initialise(struct XenDevice *xendev)
> return rc;
>
> fb_page = fb->c.page;
> - rc = xenfb_configure_fb(fb, videoram * 1024 * 1024U,
> + rc = xenfb_configure_fb(fb, videoram * M_BYTE,
> fb_page->width, fb_page->height, fb_page->depth,
> fb_page->mem_length, 0, fb_page->line_length);
> if (rc != 0)
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Thanks,
--
Anthony PERARD
^ permalink raw reply [flat|nested] 40+ messages in thread