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From: "Emilio G. Cota" <cota@braap.org>
To: Michael Clark <mjc@sifive.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups
Date: Tue, 6 Mar 2018 18:47:42 -0500	[thread overview]
Message-ID: <20180306234742.GA26112@flamenco> (raw)
In-Reply-To: <CAHNT7NsqMQr9hmFN2wBo+CevLjD=X-9UTeDCoEfg_GVEvtJ1pw@mail.gmail.com>

On Wed, Mar 07, 2018 at 12:07:18 +1300, Michael Clark wrote:
> BTW Apologies for the duplicate emails. I'm still getting to grips with the
> git-sendemail workflow and was using a sed script to Add Cc's which munged
> the headers as it didn't take into account Subject lines flowing to two
> lines. I guess I can just include Cc: in the commit message? and
> git-format-patch will handle it for me? or I just should how to use
> git-publish...

I don't have experience with git-publish. The following two suggestions
might help though:

- Yes, add Cc's to individual patches -- those are picked up by send-email.
  That also applies to the cover letter, although note that if
  you use --compose then Cc's won't be picked up. Instead, just write
  the cover letter into a 0000-$cover.patch (with Cc's in there)
  and do not use --compose.

- Use send-email's --dry-run option to make sure everything looks good
  without actually sending any emails.

> I still have to work on Igor's requested change to CPU initializer
> declarations, and i'd also like to get the patch in that fixes fmin/fmax
> test failures using the riscv-tests testsuite by implementing IEEE-754
> minimumNumber/maximumNumber. I'll try to get a patch onto the list before
> soft-freeze. I dropped the patch which was in an earlier version of our
> port patch series due to a conflict with changes in softfloat (conversion
> of minmax from a macro to a static function iirc).

Note that if you're fixing a bug (and the fmin/fmax patch qualifies),
you can definitely get it merged post-soft-freeze.

		E.

  reply	other threads:[~2018-03-06 23:47 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-06 20:43 [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 01/22] RISC-V: Make virt create_fdt interface consistent Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 02/22] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-03-06 22:56   ` Philippe Mathieu-Daudé
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 03/22] RISC-V: Make virt board description match spike Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 04/22] RISC-V: Use ROM base address and size from memory Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 05/22] RISC-V: Remove redundant identity_translate from Michael Clark
2018-03-06 23:00   ` Philippe Mathieu-Daudé
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code and Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from Michael Clark
     [not found]   ` <8787c302-b90a-df1f-9eb3-3ee16022a92e@amsat.org>
2018-03-07  4:14     ` Michael Clark
2018-03-07  4:30       ` Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure the emulated rom has space for Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in Michael Clark
2018-03-06 23:09   ` Philippe Mathieu-Daudé
2018-03-07  4:17     ` Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance Michael Clark
2018-03-09  3:54   ` Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in atomic pte Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 17/22] RISC-V: Ingore satp writes and return 0 for reads Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with Michael Clark
2018-03-06 23:09   ` Philippe Mathieu-Daudé
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48 Michael Clark
2018-03-06 20:43 ` [Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional Michael Clark
2018-03-06 23:07 ` [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups Michael Clark
2018-03-06 23:47   ` Emilio G. Cota [this message]
2018-03-07  0:00     ` Michael Clark
2018-03-07 17:40       ` Emilio G. Cota

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