qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 08/25] aarch64-linux-user: Remove struct target_aux_context
Date: Fri,  9 Mar 2018 17:26:05 +0000	[thread overview]
Message-ID: <20180309172622.4277-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180309172622.4277-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

This changes the qemu signal frame layout to be more like the kernel's,
in that the various records are dynamically allocated rather than fixed
in place by a structure.

For now, all of the allocation is out of uc.tuc_mcontext.__reserved,
so the allocation is actually trivial.  That will change with SVE support.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180303143823.27055-4-richard.henderson@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/signal.c | 89 ++++++++++++++++++++++++++++++++++++-----------------
 1 file changed, 61 insertions(+), 28 deletions(-)

diff --git a/linux-user/signal.c b/linux-user/signal.c
index 761d6acbf3..0f2b155c33 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1446,20 +1446,12 @@ struct target_fpsimd_context {
     uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */
 };
 
-/*
- * Auxiliary context saved in the sigcontext.__reserved array. Not exported to
- * user space as it will change with the addition of new context. User space
- * should check the magic/size information.
- */
-struct target_aux_context {
-    struct target_fpsimd_context fpsimd;
-    /* additional context to be added before "end" */
-    struct target_aarch64_ctx end;
-};
-
 struct target_rt_sigframe {
     struct target_siginfo info;
     struct target_ucontext uc;
+};
+
+struct target_rt_frame_record {
     uint64_t fp;
     uint64_t lr;
     uint32_t tramp[2];
@@ -1565,20 +1557,47 @@ static void target_restore_fpsimd_record(CPUARMState *env,
 static int target_restore_sigframe(CPUARMState *env,
                                    struct target_rt_sigframe *sf)
 {
-    struct target_aux_context *aux
-        = (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved;
-    uint32_t magic, size;
+    struct target_aarch64_ctx *ctx;
+    struct target_fpsimd_context *fpsimd = NULL;
 
     target_restore_general_frame(env, sf);
 
-    __get_user(magic, &aux->fpsimd.head.magic);
-    __get_user(size, &aux->fpsimd.head.size);
-    if (magic == TARGET_FPSIMD_MAGIC
-        && size == sizeof(struct target_fpsimd_context)) {
-        target_restore_fpsimd_record(env, &aux->fpsimd);
-    } else {
+    ctx = (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved;
+    while (ctx) {
+        uint32_t magic, size;
+
+        __get_user(magic, &ctx->magic);
+        __get_user(size, &ctx->size);
+        switch (magic) {
+        case 0:
+            if (size != 0) {
+                return 1;
+            }
+            ctx = NULL;
+            continue;
+
+        case TARGET_FPSIMD_MAGIC:
+            if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
+                return 1;
+            }
+            fpsimd = (struct target_fpsimd_context *)ctx;
+            break;
+
+        default:
+            /* Unknown record -- we certainly didn't generate it.
+             * Did we in fact get out of sync?
+             */
+            return 1;
+        }
+        ctx = (void *)ctx + size;
+    }
+
+    /* Require FPSIMD always.  */
+    if (!fpsimd) {
         return 1;
     }
+    target_restore_fpsimd_record(env, fpsimd);
+
     return 0;
 }
 
@@ -1604,20 +1623,33 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
                                target_siginfo_t *info, target_sigset_t *set,
                                CPUARMState *env)
 {
+    int size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved);
+    int fpsimd_ofs, end1_ofs, fr_ofs;
     struct target_rt_sigframe *frame;
-    struct target_aux_context *aux;
+    struct target_rt_frame_record *fr;
     abi_ulong frame_addr, return_addr;
 
+    fpsimd_ofs = size;
+    size += sizeof(struct target_fpsimd_context);
+    end1_ofs = size;
+    size += sizeof(struct target_aarch64_ctx);
+    fr_ofs = size;
+    size += sizeof(struct target_rt_frame_record);
+
     frame_addr = get_sigframe(ka, env);
     trace_user_setup_frame(env, frame_addr);
     if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
         goto give_sigsegv;
     }
-    aux = (struct target_aux_context *)frame->uc.tuc_mcontext.__reserved;
 
     target_setup_general_frame(frame, env, set);
-    target_setup_fpsimd_record(&aux->fpsimd, env);
-    target_setup_end_record(&aux->end);
+    target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env);
+    target_setup_end_record((void *)frame + end1_ofs);
+
+    /* Set up the stack frame for unwinding.  */
+    fr = (void *)frame + fr_ofs;
+    __put_user(env->xregs[29], &fr->fp);
+    __put_user(env->xregs[30], &fr->lr);
 
     if (ka->sa_flags & TARGET_SA_RESTORER) {
         return_addr = ka->sa_restorer;
@@ -1627,13 +1659,14 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
          * Since these are instructions they need to be put as little-endian
          * regardless of target default or current CPU endianness.
          */
-        __put_user_e(0xd2801168, &frame->tramp[0], le);
-        __put_user_e(0xd4000001, &frame->tramp[1], le);
-        return_addr = frame_addr + offsetof(struct target_rt_sigframe, tramp);
+        __put_user_e(0xd2801168, &fr->tramp[0], le);
+        __put_user_e(0xd4000001, &fr->tramp[1], le);
+        return_addr = frame_addr + fr_ofs
+            + offsetof(struct target_rt_frame_record, tramp);
     }
     env->xregs[0] = usig;
     env->xregs[31] = frame_addr;
-    env->xregs[29] = env->xregs[31] + offsetof(struct target_rt_sigframe, fp);
+    env->xregs[29] = frame_addr + fr_ofs;
     env->pc = ka->_sa_handler;
     env->xregs[30] = return_addr;
     if (info) {
-- 
2.16.2

  parent reply	other threads:[~2018-03-09 17:26 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-09 17:25 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
2018-03-09 17:25 ` [Qemu-devel] [PULL 01/25] target/arm: Add a core count property Peter Maydell
2018-03-09 17:25 ` [Qemu-devel] [PULL 02/25] hw/arm: Set the core count for Xilinx's ZynqMP Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 03/25] pci: Add support for Designware IP block Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 04/25] i.MX: Add i.MX7 SOC implementation Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 05/25] Implement support for i.MX7 Sabre board Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 06/25] linux-user: Implement aarch64 PR_SVE_SET/GET_VL Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 07/25] aarch64-linux-user: Split out helpers for guest signal handling Peter Maydell
2018-03-09 17:26 ` Peter Maydell [this message]
2018-03-09 17:26 ` [Qemu-devel] [PULL 09/25] aarch64-linux-user: Add support for EXTRA signal frame records Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 10/25] aarch64-linux-user: Add support for SVE " Peter Maydell
2018-04-06 18:12   ` Peter Maydell
2018-04-06 18:14     ` Peter Maydell
2018-04-09  8:18     ` Richard Henderson
2018-03-09 17:26 ` [Qemu-devel] [PULL 11/25] hw/arm: Use more CONFIG switches for the object files Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 12/25] arm: fix load ELF error leak Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 13/25] arm: avoid heap-buffer-overflow in load_aarch64_image Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 14/25] target/arm: Query host CPU features on-demand at instance init Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 15/25] target/arm: Move definition of 'host' cpu type into cpu.c Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 16/25] target/arm: Add "-cpu max" support Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 17/25] target/arm: Make 'any' CPU just an alias for 'max' Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 18/25] hw/arm/virt: Add "max" to the list of CPU types "virt" supports Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 19/25] hw/arm/virt: Support -machine gic-version=max Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 20/25] sdcard: Do not trace CMD55, except when we already expect an ACMD Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 21/25] sdcard: Display command name when tracing CMD/ACMD Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 22/25] sdcard: Display which protocol is used when tracing (SD or SPI) Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 23/25] sdcard: Add the Tuning Command (CMD19) Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 24/25] sdhci: Fix a typo in comment Peter Maydell
2018-03-09 17:26 ` [Qemu-devel] [PULL 25/25] MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard) Peter Maydell
2018-03-12 13:21 ` [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180309172622.4277-9-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).