From: Eduardo Habkost <ehabkost@redhat.com>
To: Babu Moger <babu.moger@amd.com>
Cc: pbonzini@redhat.com, rth@twiddle.net, rkrcmar@redhat.com,
Thomas.Lendacky@amd.com, brijesh.singh@amd.com,
kvm@vger.kernel.org, kash@tripleback.net, mtosatti@redhat.com,
Gary.Hook@amd.com, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 1/5] target/i386: Generalize some of the macro definitions
Date: Thu, 15 Mar 2018 16:07:53 -0300 [thread overview]
Message-ID: <20180315190753.GG28578@localhost.localdomain> (raw)
In-Reply-To: <1520888449-4352-2-git-send-email-babu.moger@amd.com>
Hi,
Sorry for not reviewing the previous versions of this series
(making it miss soft freeze).
On Mon, Mar 12, 2018 at 05:00:45PM -0400, Babu Moger wrote:
> Generalize some of the macro definitions which are generic cache
> properties that are common between CPUID 4 and CPUID 0x8000001D
> in preparation for adding support for 0x8000001D.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> target/i386/cpu.c | 52 ++++++++++++++++++++++++++--------------------------
> 1 file changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index b5e431e..42dd381 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -66,22 +66,22 @@
> #define CPUID_2_L3_16MB_16WAY_64B 0x4d
>
>
> -/* CPUID Leaf 4 constants: */
> +/* Cache specific constants: */
We have too many CPUID leaves that describe caches, so I would
like to explicitly document on which CPUID leaves these macros
can be used. I suggest:
/* Macros for CPUID[4] and CPUID[0x8000001D] */
>
> /* EAX: */
> -#define CPUID_4_TYPE_DCACHE 1
> -#define CPUID_4_TYPE_ICACHE 2
> -#define CPUID_4_TYPE_UNIFIED 3
> +#define TYPE_DCACHE 1
> +#define TYPE_ICACHE 2
> +#define TYPE_UNIFIED 3
TYPE_* can be confused with QOM type names, I'd use something
else. Maybe CACHE_TYPE_D, CACHE_TYPE_I, CACHE_TYPE_UNIFIED?
>
> -#define CPUID_4_LEVEL(l) ((l) << 5)
> +#define CACHE_LEVEL(l) ((l) << 5)
>
> -#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
> -#define CPUID_4_FULLY_ASSOC (1 << 9)
> +#define CACHE_SELF_INIT_LEVEL (1 << 8)
> +#define CACHE_FULLY_ASSOC (1 << 9)
>
> /* EDX: */
> -#define CPUID_4_NO_INVD_SHARING (1 << 0)
> -#define CPUID_4_INCLUSIVE (1 << 1)
> -#define CPUID_4_COMPLEX_IDX (1 << 2)
> +#define CACHE_NO_INVD_SHARING (1 << 0)
> +#define CACHE_INCLUSIVE (1 << 1)
> +#define CACHE_COMPLEX_IDX (1 << 2)
>
> #define ASSOC_FULL 0xFF
>
[...]
--
Eduardo
next prev parent reply other threads:[~2018-03-15 19:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 21:00 [Qemu-devel] [PATCH v4 0/5] Enable TOPOEXT to support hyperthreading on AMD CPU Babu Moger
2018-03-12 21:00 ` [Qemu-devel] [PATCH v4 1/5] target/i386: Generalize some of the macro definitions Babu Moger
2018-03-15 19:07 ` Eduardo Habkost [this message]
2018-03-12 21:00 ` [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information Babu Moger
2018-03-15 19:04 ` Eduardo Habkost
2018-03-16 18:00 ` Eduardo Habkost
2018-03-20 17:25 ` Moger, Babu
2018-03-20 17:54 ` Eduardo Habkost
2018-03-20 19:20 ` Moger, Babu
2018-03-21 15:58 ` Moger, Babu
2018-03-21 17:09 ` Eduardo Habkost
2018-03-21 17:12 ` Kash Pande
2018-03-21 17:47 ` Moger, Babu
2018-03-21 18:15 ` Eduardo Habkost
2018-03-21 20:07 ` Moger, Babu
2018-03-21 20:29 ` Eduardo Habkost
2018-03-27 21:36 ` Moger, Babu
2018-03-12 21:00 ` [Qemu-devel] [PATCH v4 3/5] target/i386: Add support for CPUID_8000_001E for AMD Babu Moger
2018-03-12 21:00 ` [Qemu-devel] [PATCH v4 4/5] target/i386: Enable TOPOEXT feature on AMD EPYC CPU Babu Moger
2018-03-12 21:00 ` [Qemu-devel] [PATCH v4 5/5] target/i386: Remove generic SMT thread check Babu Moger
2018-03-13 21:39 ` [Qemu-devel] [PATCH v4 0/5] Enable TOPOEXT to support hyperthreading on AMD CPU Kash Pande
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