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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
Date: Mon, 19 Mar 2018 18:34:09 +0000	[thread overview]
Message-ID: <20180319183415.1976-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180319183415.1976-1-peter.maydell@linaro.org>

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e21a92f972..9319b12fcd 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -729,6 +729,11 @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

  parent reply	other threads:[~2018-03-19 18:34 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-19 18:34 [Qemu-devel] [PULL 00/13] target-arm queue Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64 Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update() Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 Peter Maydell
2018-03-19 18:34 ` Peter Maydell [this message]
2018-03-19 18:34 ` [Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386 Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837 Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type Peter Maydell
2018-03-19 18:34 ` [Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs Peter Maydell
2018-03-20  9:51 ` [Qemu-devel] [PULL 00/13] target-arm queue Peter Maydell

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