From: "Emilio G. Cota" <cota@braap.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, patches@groups.riscv.org, mjc@sifive.com
Subject: Re: [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops
Date: Tue, 27 Mar 2018 01:45:59 -0400 [thread overview]
Message-ID: <20180327054559.GA1666@flamenco> (raw)
In-Reply-To: <20180327034757.3432-1-richard.henderson@linaro.org>
On Tue, Mar 27, 2018 at 11:47:57 +0800, Richard Henderson wrote:
> Failure to do so results in the tcg optimizer sign-extending
> any constant fold from 32-bits. This turns out to be visible
> in the RISC-V testsuite using a host that emits these opcodes
> (e.g. any non-x86_64).
>
> Reported-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
E.
next prev parent reply other threads:[~2018-03-27 5:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-27 3:47 [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops Richard Henderson
2018-03-27 5:45 ` Emilio G. Cota [this message]
2018-03-27 14:39 ` Philippe Mathieu-Daudé
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