[Qemu-devel] [PULL for-2.12 0/1] tcg mul[us]h fix

[Qemu-devel] [PULL for-2.12 0/1] tcg mul[us]h fix

[Richard Henderson]

This is material for stable as well.


r~


The following changes since commit fa3704d87720d7049d483ff669b9e2ff991e7658:

  Update version for v2.12.0-rc1 release (2018-03-27 22:04:23 +0100)

are available in the Git repository at:

  git://github.com/rth7680/qemu.git tags/pull-tcg-20180328

for you to fetch changes up to f2f1dde75160cac6ede330f3db50dc817d01a2d6:

  tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops (2018-03-28 12:45:16 +0800)

----------------------------------------------------------------
Fix muluh_i64 and mulsh_i64 flags

----------------------------------------------------------------
Richard Henderson (1):
      tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops

 tcg/tcg-opc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

[Qemu-devel] [PULL 1/1] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops

[Richard Henderson]

Failure to do so results in the tcg optimizer sign-extending
any constant fold from 32-bits.  This turns out to be visible
in the RISC-V testsuite using a host that emits these opcodes
(e.g. any non-x86_64).

Reported-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-opc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index d81a6c4535..e3a43aabb6 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -182,8 +182,8 @@ DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
-DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
-DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
+DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
+DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
 
 #define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
 #define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
-- 
2.14.3

Re: [Qemu-devel] [PULL for-2.12 0/1] tcg mul[us]h fix

[Peter Maydell]

On 28 March 2018 at 05:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
> This is material for stable as well.
>
>
> r~
>
>
> The following changes since commit fa3704d87720d7049d483ff669b9e2ff991e7658:
>
>   Update version for v2.12.0-rc1 release (2018-03-27 22:04:23 +0100)
>
> are available in the Git repository at:
>
>   git://github.com/rth7680/qemu.git tags/pull-tcg-20180328
>
> for you to fetch changes up to f2f1dde75160cac6ede330f3db50dc817d01a2d6:
>
>   tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops (2018-03-28 12:45:16 +0800)
>
> ----------------------------------------------------------------
> Fix muluh_i64 and mulsh_i64 flags
>
> ----------------------------------------------------------------
> Richard Henderson (1):
>       tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops

Applied, thanks.

-- PMM