* [Qemu-devel] [PATCHv1 01/14] translator: merge max_insns into DisasContextBase
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 02/14] target/sh4: convert to TranslatorOps Emilio G. Cota
` (16 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
While at it, use int for both num_insns and max_insns to make
sure we have same-type comparisons.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
include/exec/translator.h | 8 ++++----
accel/tcg/translator.c | 21 ++++++++++-----------
target/alpha/translate.c | 6 ++----
target/arm/translate-a64.c | 8 +++-----
target/arm/translate.c | 9 +++------
target/hppa/translate.c | 7 ++-----
target/i386/translate.c | 5 +----
target/ppc/translate.c | 5 ++---
8 files changed, 27 insertions(+), 42 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index e2dc2a0..71e7b2c 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -58,6 +58,7 @@ typedef enum DisasJumpType {
* disassembly).
* @is_jmp: What instruction to disassemble next.
* @num_insns: Number of translated instructions (including current).
+ * @max_insns: Maximum number of instructions to be translated in this TB.
* @singlestep_enabled: "Hardware" single stepping enabled.
*
* Architecture-agnostic disassembly context.
@@ -67,7 +68,8 @@ typedef struct DisasContextBase {
target_ulong pc_first;
target_ulong pc_next;
DisasJumpType is_jmp;
- unsigned int num_insns;
+ int num_insns;
+ int max_insns;
bool singlestep_enabled;
} DisasContextBase;
@@ -76,7 +78,6 @@ typedef struct DisasContextBase {
* @init_disas_context:
* Initialize the target-specific portions of DisasContext struct.
* The generic DisasContextBase has already been initialized.
- * Return max_insns, modified as necessary by db->tb->flags.
*
* @tb_start:
* Emit any code required before the start of the main loop,
@@ -106,8 +107,7 @@ typedef struct DisasContextBase {
* Print instruction disassembly to log.
*/
typedef struct TranslatorOps {
- int (*init_disas_context)(DisasContextBase *db, CPUState *cpu,
- int max_insns);
+ void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
void (*tb_start)(DisasContextBase *db, CPUState *cpu);
void (*insn_start)(DisasContextBase *db, CPUState *cpu);
bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu,
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 23c6602..0f9dca9 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -34,8 +34,6 @@ void translator_loop_temp_check(DisasContextBase *db)
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
CPUState *cpu, TranslationBlock *tb)
{
- int max_insns;
-
/* Initialize DisasContext */
db->tb = tb;
db->pc_first = tb->pc;
@@ -45,18 +43,18 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
db->singlestep_enabled = cpu->singlestep_enabled;
/* Instruction counting */
- max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
+ db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
+ if (db->max_insns == 0) {
+ db->max_insns = CF_COUNT_MASK;
}
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
+ if (db->max_insns > TCG_MAX_INSNS) {
+ db->max_insns = TCG_MAX_INSNS;
}
if (db->singlestep_enabled || singlestep) {
- max_insns = 1;
+ db->max_insns = 1;
}
- max_insns = ops->init_disas_context(db, cpu, max_insns);
+ ops->init_disas_context(db, cpu);
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
/* Reset the temp count so that we can identify leaks */
@@ -95,7 +93,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
update db->pc_next and db->is_jmp to indicate what should be
done next -- either exiting this loop or locate the start of
the next instruction. */
- if (db->num_insns == max_insns && (tb_cflags(db->tb) & CF_LAST_IO)) {
+ if (db->num_insns == db->max_insns
+ && (tb_cflags(db->tb) & CF_LAST_IO)) {
/* Accept I/O on the last instruction. */
gen_io_start();
ops->translate_insn(db, cpu);
@@ -111,7 +110,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
/* Stop translation if the output buffer is full,
or we have executed all of the allowed instructions. */
- if (tcg_op_buf_full() || db->num_insns >= max_insns) {
+ if (tcg_op_buf_full() || db->num_insns >= db->max_insns) {
db->is_jmp = DISAS_TOO_MANY;
break;
}
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 73a1b5e..15eca71 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2919,8 +2919,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
-static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cpu, int max_insns)
+static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUAlphaState *env = cpu->env_ptr;
@@ -2959,8 +2958,7 @@ static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
mask = TARGET_PAGE_MASK;
}
bound = -(ctx->base.pc_first | mask) / 4;
-
- return MIN(max_insns, bound);
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1c88539..55f00a6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -12009,8 +12009,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s);
}
-static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cpu, int max_insns)
+static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
+ CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cpu->env_ptr;
@@ -12073,11 +12073,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
if (dc->ss_active) {
bound = 1;
}
- max_insns = MIN(max_insns, bound);
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
init_tmp_a64_array(dc);
-
- return max_insns;
}
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1270022..9284975 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11975,8 +11975,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
return !thumb_insn_is_16bit(s, insn);
}
-static int arm_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cs, int max_insns)
+static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
@@ -12038,14 +12037,14 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
/* If architectural single step active, limit to 1. */
if (is_singlestepping(dc)) {
- max_insns = 1;
+ dc->base.max_insns = 1;
}
/* ARM is a fixed-length ISA. Bound the number of insns to execute
to those left on the page. */
if (!dc->thumb) {
int bound = (dc->next_page_start - dc->base.pc_first) / 4;
- max_insns = MIN(max_insns, bound);
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
}
cpu_F0s = tcg_temp_new_i32();
@@ -12056,8 +12055,6 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
cpu_V1 = cpu_F1d;
/* FIXME: cpu_M0 can probably be the same as cpu_V0. */
cpu_M0 = tcg_temp_new_i64();
-
- return max_insns;
}
static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 6499b39..1afca76 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4685,8 +4685,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
return gen_illegal(ctx);
}
-static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cs, int max_insns)
+static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
int bound;
@@ -4716,14 +4715,12 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
/* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- bound = MIN(max_insns, bound);
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
ctx->ntempr = 0;
ctx->ntempl = 0;
memset(ctx->tempr, 0, sizeof(ctx->tempr));
memset(ctx->templ, 0, sizeof(ctx->templ));
-
- return bound;
}
static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 0135415..a462913 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8400,8 +8400,7 @@ void tcg_x86_init(void)
}
}
-static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
- int max_insns)
+static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUX86State *env = cpu->env_ptr;
@@ -8468,8 +8467,6 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
cpu_ptr0 = tcg_temp_new_ptr();
cpu_ptr1 = tcg_temp_new_ptr();
cpu_cc_srcT = tcg_temp_local_new();
-
- return max_insns;
}
static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0a0c090..b5a0dd7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7207,8 +7207,7 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
#endif
}
-static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
- CPUState *cs, int max_insns)
+static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUPPCState *env = cs->env_ptr;
@@ -7274,7 +7273,7 @@ static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
#endif
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- return MIN(max_insns, bound);
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 02/14] target/sh4: convert to TranslatorOps
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 01/14] translator: merge max_insns into DisasContextBase Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 03/14] target/sparc: convert to DisasJumpType Emilio G. Cota
` (15 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno
This was fairly straightforward since it had already been converted
to DisasContextBase; just had to add TARGET_TOO_MANY to the switch
in tb_stop.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sh4/translate.c | 171 +++++++++++++++++++++++++------------------------
1 file changed, 86 insertions(+), 85 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 012156b..58bdfeb 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2258,126 +2258,127 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
}
#endif
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUSH4State *env = cs->env_ptr;
- DisasContext ctx;
- target_ulong pc_start;
- int num_insns;
- int max_insns;
-
- pc_start = tb->pc;
- ctx.base.pc_next = pc_start;
- ctx.tbflags = (uint32_t)tb->flags;
- ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
- ctx.base.is_jmp = DISAS_NEXT;
- ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
+ int bound;
+
+ ctx->tbflags = (uint32_t)ctx->base.tb->flags;
+ ctx->envflags = ctx->base.tb->flags & TB_FLAG_ENVFLAGS_MASK;
+ ctx->memidx = (ctx->tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
- ctx.delayed_pc = -1; /* use delayed pc from env pointer */
- ctx.base.tb = tb;
- ctx.base.singlestep_enabled = cs->singlestep_enabled;
- ctx.features = env->features;
- ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
- ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&
- (ctx.tbflags & (1 << SR_RB))) * 0x10;
- ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;
-
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- max_insns = MIN(max_insns, TCG_MAX_INSNS);
+ ctx->delayed_pc = -1; /* use delayed pc from env pointer */
+ ctx->features = env->features;
+ ctx->has_movcal = (ctx->tbflags & TB_FLAG_PENDING_MOVCA);
+ ctx->gbank = ((ctx->tbflags & (1 << SR_MD)) &&
+ (ctx->tbflags & (1 << SR_RB))) * 0x10;
+ ctx->fbank = ctx->tbflags & FPSCR_FR ? 0x10 : 0;
/* Since the ISA is fixed-width, we can bound by the number
of instructions remaining on the page. */
- num_insns = -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2;
- max_insns = MIN(max_insns, num_insns);
-
- /* Single stepping means just that. */
- if (ctx.base.singlestep_enabled || singlestep) {
- max_insns = 1;
- }
-
- gen_tb_start(tb);
- num_insns = 0;
+ bound = -(ctx->base.pc_next | TARGET_PAGE_MASK) / 2;
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+}
+static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
+{
#ifdef CONFIG_USER_ONLY
- if (ctx.tbflags & GUSA_MASK) {
- num_insns = decode_gusa(&ctx, env, &max_insns);
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ CPUSH4State *env = cs->env_ptr;
+
+ if (ctx->tbflags & GUSA_MASK) {
+ ctx->base.num_insns = decode_gusa(ctx, env, &ctx->base.max_insns);
}
#endif
+}
- while (ctx.base.is_jmp == DISAS_NEXT
- && num_insns < max_insns
- && !tcg_op_buf_full()) {
- tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags);
- num_insns++;
+static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
- /* We have hit a breakpoint - make sure PC is up-to-date */
- gen_save_cpu_state(&ctx, true);
- gen_helper_debug(cpu_env);
- ctx.base.is_jmp = DISAS_NORETURN;
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- ctx.base.pc_next += 2;
- break;
- }
+ tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);
+}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
- decode_opc(&ctx);
- ctx.base.pc_next += 2;
- }
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
- }
+ /* We have hit a breakpoint - make sure PC is up-to-date */
+ gen_save_cpu_state(ctx, true);
+ gen_helper_debug(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ ctx->base.pc_next += 2;
+ return true;
+}
+
+static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ CPUSH4State *env = cs->env_ptr;
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- if (ctx.tbflags & GUSA_EXCLUSIVE) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ decode_opc(ctx);
+ ctx->base.pc_next += 2;
+}
+
+static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
+ if (ctx->tbflags & GUSA_EXCLUSIVE) {
/* Ending the region of exclusivity. Clear the bits. */
- ctx.envflags &= ~GUSA_MASK;
+ ctx->envflags &= ~GUSA_MASK;
}
- switch (ctx.base.is_jmp) {
+ switch (ctx->base.is_jmp) {
case DISAS_STOP:
- gen_save_cpu_state(&ctx, true);
- if (ctx.base.singlestep_enabled) {
+ gen_save_cpu_state(ctx, true);
+ if (ctx->base.singlestep_enabled) {
gen_helper_debug(cpu_env);
} else {
tcg_gen_exit_tb(0);
}
break;
case DISAS_NEXT:
- gen_save_cpu_state(&ctx, false);
- gen_goto_tb(&ctx, 0, ctx.base.pc_next);
+ case DISAS_TOO_MANY:
+ gen_save_cpu_state(ctx, false);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NORETURN:
break;
default:
g_assert_not_reached();
}
+}
- gen_tb_end(tb, num_insns);
+static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */
+ log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
+}
- tb->size = ctx.base.pc_next - pc_start;
- tb->icount = num_insns;
+static const TranslatorOps sh4_tr_ops = {
+ .init_disas_context = sh4_tr_init_disas_context,
+ .tb_start = sh4_tr_tb_start,
+ .insn_start = sh4_tr_insn_start,
+ .breakpoint_check = sh4_tr_breakpoint_check,
+ .translate_insn = sh4_tr_translate_insn,
+ .tb_stop = sh4_tr_tb_stop,
+ .disas_log = sh4_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+{
+ DisasContext ctx;
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- qemu_log_lock();
- qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
- log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+ translator_loop(&sh4_tr_ops, &ctx.base, cs, tb);
}
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 03/14] target/sparc: convert to DisasJumpType
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 01/14] translator: merge max_insns into DisasContextBase Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 02/14] target/sh4: convert to TranslatorOps Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 04/14] target/sparc: convert to DisasContextBase Emilio G. Cota
` (14 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Artyom Tarasenko
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sparc/translate.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 71e0853..730e25d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -30,6 +30,7 @@
#include "exec/helper-gen.h"
#include "trace-tcg.h"
+#include "exec/translator.h"
#include "exec/log.h"
#include "asi.h"
@@ -69,7 +70,7 @@ typedef struct DisasContext {
target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
- int is_br;
+ DisasJumpType is_jmp;
int mem_idx;
bool fpu_enabled;
bool address_mask_32bit;
@@ -995,7 +996,7 @@ static void gen_branch_a(DisasContext *dc, target_ulong pc1)
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
}
static void gen_branch_n(DisasContext *dc, target_ulong pc1)
@@ -1078,7 +1079,7 @@ static void gen_exception(DisasContext *dc, int which)
t = tcg_const_i32(which);
gen_helper_raise_exception(cpu_env, t);
tcg_temp_free_i32(t);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
}
static void gen_check_align(TCGv addr, int mask)
@@ -3346,7 +3347,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (cond == 8) {
/* An unconditional trap ends the TB. */
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
goto jmp_insn;
} else {
/* A conditional trap falls through to the next insn. */
@@ -4326,7 +4327,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
break;
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
@@ -4335,7 +4336,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
break;
case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
@@ -4463,7 +4464,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
#endif
}
break;
@@ -4619,7 +4620,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
break;
case 1: // htstate
// XXX gen_op_wrhtstate();
@@ -5685,7 +5686,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else if (dc->npc == JUMP_PC) {
/* we can do a static jump */
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
} else {
dc->pc = dc->npc;
dc->npc = dc->npc + 4;
@@ -5747,6 +5748,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
pc_start = tb->pc;
dc->pc = pc_start;
last_pc = dc->pc;
+ dc->is_jmp = DISAS_NEXT;
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
@@ -5791,7 +5793,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
}
gen_helper_debug(cpu_env);
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
goto exit_gen_loop;
}
@@ -5803,8 +5805,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
disas_sparc_insn(dc, insn);
- if (dc->is_br)
+ if (dc->is_jmp == DISAS_NORETURN) {
break;
+ }
/* if the next PC is different, we abort now */
if (dc->pc != (last_pc + 4))
break;
@@ -5825,7 +5828,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (!dc->is_br) {
+ if (dc->is_jmp != DISAS_NORETURN) {
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 04/14] target/sparc: convert to DisasContextBase
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (2 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 03/14] target/sparc: convert to DisasJumpType Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 05/14] target/sparc: convert to TranslatorOps Emilio G. Cota
` (13 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Artyom Tarasenko
Notes:
- pc and npc are left unmodified, since they can point to out-of-TB
jump targets.
- Got rid of last_pc in gen_intermediate_code(), using base.pc_next
instead. Only update pc_next (1) on a breakpoint (so that tb->size
includes the insn), and (2) after reading the current instruction
from memory. This allows us to use base.pc_next in the BP check,
which is what the translator loop does.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sparc/translate.c | 92 +++++++++++++++++++++++-------------------------
1 file changed, 45 insertions(+), 47 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 730e25d..374f98d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -67,14 +67,13 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS];
#include "exec/gen-icount.h"
typedef struct DisasContext {
+ DisasContextBase base;
target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
- DisasJumpType is_jmp;
int mem_idx;
bool fpu_enabled;
bool address_mask_32bit;
- bool singlestep;
#ifndef CONFIG_USER_ONLY
bool supervisor;
#ifdef TARGET_SPARC64
@@ -83,7 +82,6 @@ typedef struct DisasContext {
#endif
uint32_t cc_op; /* current CC operation */
- struct TranslationBlock *tb;
sparc_def_t *def;
TCGv_i32 t32[3];
TCGv ttl[5];
@@ -342,13 +340,13 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
target_ulong npc)
{
- if (unlikely(s->singlestep)) {
+ if (unlikely(s->base.singlestep_enabled || singlestep)) {
return false;
}
#ifndef CONFIG_USER_ONLY
- return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
- (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
+ return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) &&
+ (npc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK);
#else
return true;
#endif
@@ -362,7 +360,7 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
tcg_gen_goto_tb(tb_num);
tcg_gen_movi_tl(cpu_pc, pc);
tcg_gen_movi_tl(cpu_npc, npc);
- tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num);
} else {
/* jump to another page: currently not optimized */
tcg_gen_movi_tl(cpu_pc, pc);
@@ -996,7 +994,7 @@ static void gen_branch_a(DisasContext *dc, target_ulong pc1)
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_branch_n(DisasContext *dc, target_ulong pc1)
@@ -1079,7 +1077,7 @@ static void gen_exception(DisasContext *dc, int which)
t = tcg_const_i32(which);
gen_helper_raise_exception(cpu_env, t);
tcg_temp_free_i32(t);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_check_align(TCGv addr, int mask)
@@ -2437,7 +2435,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
default:
/* ??? In theory, this should be raise DAE_invalid_asi.
But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
- if (tb_cflags(dc->tb) & CF_PARALLEL) {
+ if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
TCGv_i32 r_asi = tcg_const_i32(da.asi);
@@ -3347,7 +3345,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (cond == 8) {
/* An unconditional trap ends the TB. */
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
goto jmp_insn;
} else {
/* A conditional trap falls through to the next insn. */
@@ -4327,7 +4325,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
@@ -4336,7 +4334,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
@@ -4464,7 +4462,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
#endif
}
break;
@@ -4620,7 +4618,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 1: // htstate
// XXX gen_op_wrhtstate();
@@ -5686,7 +5684,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else if (dc->npc == JUMP_PC) {
/* we can do a static jump */
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
} else {
dc->pc = dc->npc;
dc->npc = dc->npc + 4;
@@ -5737,25 +5735,25 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
{
CPUSPARCState *env = cs->env_ptr;
- target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
- int num_insns;
int max_insns;
unsigned int insn;
memset(dc, 0, sizeof(DisasContext));
- dc->tb = tb;
- pc_start = tb->pc;
- dc->pc = pc_start;
- last_pc = dc->pc;
- dc->is_jmp = DISAS_NEXT;
+ dc->base.tb = tb;
+ dc->base.pc_first = tb->pc;
+ dc->base.pc_next = tb->pc;
+ dc->base.is_jmp = DISAS_NEXT;
+ dc->base.num_insns = 0;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+
+ dc->pc = dc->base.pc_first;
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
dc->def = &env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
- dc->singlestep = (cs->singlestep_enabled || singlestep);
#ifndef CONFIG_USER_ONLY
dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
#endif
@@ -5767,7 +5765,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
#endif
#endif
- num_insns = 0;
max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
@@ -5775,6 +5772,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
+ if (dc->base.singlestep_enabled || singlestep) {
+ max_insns = 1;
+ }
gen_tb_start(tb);
do {
@@ -5784,51 +5784,48 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
} else {
tcg_gen_insn_start(dc->pc, dc->npc);
}
- num_insns++;
- last_pc = dc->pc;
+ dc->base.num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
- if (dc->pc != pc_start) {
+ if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
+ if (dc->pc != dc->base.pc_first) {
save_state(dc);
}
gen_helper_debug(cpu_env);
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
+ dc->base.pc_next += 4;
goto exit_gen_loop;
}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
+ if (dc->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
insn = cpu_ldl_code(env, dc->pc);
+ dc->base.pc_next += 4;
disas_sparc_insn(dc, insn);
- if (dc->is_jmp == DISAS_NORETURN) {
+ if (dc->base.is_jmp == DISAS_NORETURN) {
break;
}
/* if the next PC is different, we abort now */
- if (dc->pc != (last_pc + 4))
+ if (dc->pc != dc->base.pc_next) {
break;
+ }
/* if we reach a page boundary, we stop generation so that the
PC of a TT_TFAULT exception is always in the right page */
if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
- /* if single step mode, we generate only one instruction and
- generate an exception */
- if (dc->singlestep) {
- break;
- }
} while (!tcg_op_buf_full() &&
- (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
- num_insns < max_insns);
+ (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) &&
+ dc->base.num_insns < max_insns);
exit_gen_loop:
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (dc->is_jmp != DISAS_NORETURN) {
+ if (dc->base.is_jmp != DISAS_NORETURN) {
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
@@ -5841,18 +5838,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
tcg_gen_exit_tb(0);
}
}
- gen_tb_end(tb, num_insns);
+ gen_tb_end(tb, dc->base.num_insns);
- tb->size = last_pc + 4 - pc_start;
- tb->icount = num_insns;
+ tb->size = dc->base.pc_next - dc->base.pc_first;
+ tb->icount = dc->base.num_insns;
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
+ && qemu_log_in_addr_range(dc->base.pc_first)) {
qemu_log_lock();
qemu_log("--------------\n");
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, last_pc + 4 - pc_start);
+ qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
+ log_target_disas(cs, dc->base.pc_first,
+ dc->base.pc_next - dc->base.pc_first);
qemu_log("\n");
qemu_log_unlock();
}
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 05/14] target/sparc: convert to TranslatorOps
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (3 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 04/14] target/sparc: convert to DisasContextBase Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 06/14] target/mips: convert to DisasJumpType Emilio G. Cota
` (12 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Artyom Tarasenko
Notes:
- Moved the cross-page check from the end of translate_insn to
init_disas_context.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sparc/translate.c | 174 +++++++++++++++++++++++------------------------
1 file changed, 86 insertions(+), 88 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 374f98d..1f8f96e 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5732,99 +5732,91 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
-void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
+static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUSPARCState *env = cs->env_ptr;
- DisasContext dc1, *dc = &dc1;
- int max_insns;
- unsigned int insn;
-
- memset(dc, 0, sizeof(DisasContext));
- dc->base.tb = tb;
- dc->base.pc_first = tb->pc;
- dc->base.pc_next = tb->pc;
- dc->base.is_jmp = DISAS_NEXT;
- dc->base.num_insns = 0;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
+ int bound;
dc->pc = dc->base.pc_first;
- dc->npc = (target_ulong) tb->cs_base;
+ dc->npc = (target_ulong)dc->base.tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
- dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
+ dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
dc->def = &env->def;
- dc->fpu_enabled = tb_fpu_enabled(tb->flags);
- dc->address_mask_32bit = tb_am_enabled(tb->flags);
+ dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
+ dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
#ifndef CONFIG_USER_ONLY
- dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
+ dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
#endif
#ifdef TARGET_SPARC64
dc->fprs_dirty = 0;
- dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
+ dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
#ifndef CONFIG_USER_ONLY
- dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
+ dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
#endif
#endif
+ /*
+ * if we reach a page boundary, we stop generation so that the
+ * PC of a TT_TFAULT exception is always in the right page
+ */
+ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
+}
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
- if (dc->base.singlestep_enabled || singlestep) {
- max_insns = 1;
- }
+static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
+{
+}
- gen_tb_start(tb);
- do {
- if (dc->npc & JUMP_PC) {
- assert(dc->jump_pc[1] == dc->pc + 4);
- tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
- } else {
- tcg_gen_insn_start(dc->pc, dc->npc);
- }
- dc->base.num_insns++;
+static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
- if (dc->pc != dc->base.pc_first) {
- save_state(dc);
- }
- gen_helper_debug(cpu_env);
- tcg_gen_exit_tb(0);
- dc->base.is_jmp = DISAS_NORETURN;
- dc->base.pc_next += 4;
- goto exit_gen_loop;
- }
+ if (dc->npc & JUMP_PC) {
+ assert(dc->jump_pc[1] == dc->pc + 4);
+ tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
+ } else {
+ tcg_gen_insn_start(dc->pc, dc->npc);
+ }
+}
- if (dc->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- insn = cpu_ldl_code(env, dc->pc);
- dc->base.pc_next += 4;
+ if (dc->pc != dc->base.pc_first) {
+ save_state(dc);
+ }
+ gen_helper_debug(cpu_env);
+ tcg_gen_exit_tb(0);
+ dc->base.is_jmp = DISAS_NORETURN;
+ /* update pc_next so that the current instruction is included in tb->size */
+ dc->base.pc_next += 4;
+ return true;
+}
- disas_sparc_insn(dc, insn);
+static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ CPUSPARCState *env = cs->env_ptr;
+ unsigned int insn;
- if (dc->base.is_jmp == DISAS_NORETURN) {
- break;
- }
- /* if the next PC is different, we abort now */
- if (dc->pc != dc->base.pc_next) {
- break;
- }
- /* if we reach a page boundary, we stop generation so that the
- PC of a TT_TFAULT exception is always in the right page */
- if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
- break;
- } while (!tcg_op_buf_full() &&
- (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) &&
- dc->base.num_insns < max_insns);
+ insn = cpu_ldl_code(env, dc->pc);
+ dc->base.pc_next += 4;
+ disas_sparc_insn(dc, insn);
- exit_gen_loop:
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+ if (dc->pc != dc->base.pc_next) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
}
+}
+
+static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
if (dc->base.is_jmp != DISAS_NORETURN) {
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
@@ -5838,23 +5830,29 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
tcg_gen_exit_tb(0);
}
}
- gen_tb_end(tb, dc->base.num_insns);
-
- tb->size = dc->base.pc_next - dc->base.pc_first;
- tb->icount = dc->base.num_insns;
-
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(dc->base.pc_first)) {
- qemu_log_lock();
- qemu_log("--------------\n");
- qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
- log_target_disas(cs, dc->base.pc_first,
- dc->base.pc_next - dc->base.pc_first);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+}
+
+static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
+{
+ qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+ log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps sparc_tr_ops = {
+ .init_disas_context = sparc_tr_init_disas_context,
+ .tb_start = sparc_tr_tb_start,
+ .insn_start = sparc_tr_insn_start,
+ .breakpoint_check = sparc_tr_breakpoint_check,
+ .translate_insn = sparc_tr_translate_insn,
+ .tb_stop = sparc_tr_tb_stop,
+ .disas_log = sparc_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+{
+ DisasContext dc = {};
+
+ translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
}
void sparc_tcg_init(void)
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 06/14] target/mips: convert to DisasJumpType
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (4 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 05/14] target/sparc: convert to TranslatorOps Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-07 23:15 ` Philippe Mathieu-Daudé
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 07/14] target/mips: convert to DisasContextBase Emilio G. Cota
` (11 subsequent siblings)
17 siblings, 1 reply; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno, Yongbok Kim
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/mips/translate.c | 186 +++++++++++++++++++++++-------------------------
1 file changed, 91 insertions(+), 95 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d05ee67..a133205 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -36,6 +36,7 @@
#include "target/mips/trace.h"
#include "trace-tcg.h"
+#include "exec/translator.h"
#include "exec/log.h"
#define MIPS_DEBUG_DISAS 0
@@ -1439,7 +1440,7 @@ typedef struct DisasContext {
int mem_idx;
TCGMemOp default_tcg_memop_mask;
uint32_t hflags, saved_hflags;
- int bstate;
+ DisasJumpType is_jmp;
target_ulong btarget;
bool ulri;
int kscrexist;
@@ -1460,13 +1461,8 @@ typedef struct DisasContext {
bool abs2008;
} DisasContext;
-enum {
- BS_NONE = 0, /* We go out of the TB without reaching a branch or an
- * exception condition */
- BS_STOP = 1, /* We want to stop translation for any reason */
- BS_BRANCH = 2, /* We reached a branch condition */
- BS_EXCP = 3, /* We reached an exception condition */
-};
+#define DISAS_STOP DISAS_TARGET_0
+#define DISAS_EXCP DISAS_TARGET_1
static const char * const regnames[] = {
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
@@ -1639,7 +1635,7 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
gen_helper_raise_exception_err(cpu_env, texcp, terr);
tcg_temp_free_i32(terr);
tcg_temp_free_i32(texcp);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
}
static inline void generate_exception(DisasContext *ctx, int excp)
@@ -5334,10 +5330,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_io_end();
}
/* Break the TB to be able to take timer interrupts immediately
- after reading count. BS_STOP isn't sufficient, we need to ensure
- we break completely out of translated code. */
+ after reading count. DISAS_STOP isn't sufficient, we need to
+ ensure we break completely out of translated code. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -5905,7 +5901,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
rn = "PageGrain";
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 2:
CP0_CHECK(ctx->sc);
@@ -5966,7 +5962,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "HWREna";
break;
default:
@@ -6028,30 +6024,30 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
- /* BS_STOP isn't good enough here, hflags may have changed. */
+ /* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "SRSMap";
break;
default:
@@ -6063,11 +6059,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
- /* Stop translation as we may have triggered an interrupt. BS_STOP
- * isn't sufficient, we need to ensure we break out of translated
- * code to check for pending interrupts. */
+ /* Stop translation as we may have triggered an interrupt.
+ * DISAS_STOP isn't sufficient, we need to ensure we break out of
+ * translated code to check for pending interrupts. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Cause";
break;
default:
@@ -6105,7 +6101,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config0(cpu_env, arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 1:
/* ignored, read only */
@@ -6115,24 +6111,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config2(cpu_env, arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 3:
gen_helper_mtc0_config3(cpu_env, arg);
rn = "Config3";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 4:
gen_helper_mtc0_config4(cpu_env, arg);
rn = "Config4";
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 5:
gen_helper_mtc0_config5(cpu_env, arg);
rn = "Config5";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
case 6:
@@ -6221,35 +6217,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
- /* BS_STOP isn't good enough here, hflags may have changed. */
+ /* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Debug";
break;
case 1:
// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 3:
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "TraceBPC";
goto cp0_unimplemented;
default:
@@ -6309,7 +6305,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "ErrCtl";
break;
default:
@@ -6402,10 +6398,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
- /* BS_STOP isn't sufficient, we need to ensure we break out of
+ /* DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
}
return;
@@ -6686,10 +6682,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_io_end();
}
/* Break the TB to be able to take timer interrupts immediately
- after reading count. BS_STOP isn't sufficient, we need to ensure
- we break completely out of translated code. */
+ after reading count. DISAS_STOP isn't sufficient, we need to
+ ensure we break completely out of translated code. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -7301,7 +7297,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "HWREna";
break;
default:
@@ -7337,7 +7333,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 10:
switch (sel) {
@@ -7360,37 +7356,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 12:
switch (sel) {
case 0:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
- /* BS_STOP isn't good enough here, hflags may have changed. */
+ /* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "SRSMap";
break;
default:
@@ -7402,11 +7398,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
- /* Stop translation as we may have triggered an intetrupt. BS_STOP
- * isn't sufficient, we need to ensure we break out of translated
- * code to check for pending interrupts. */
+ /* Stop translation as we may have triggered an intetrupt.
+ * DISAS_STOP isn't sufficient, we need to ensure we break out of
+ * translated code to check for pending interrupts. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Cause";
break;
default:
@@ -7444,7 +7440,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config0(cpu_env, arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 1:
/* ignored, read only */
@@ -7454,13 +7450,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config2(cpu_env, arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 3:
gen_helper_mtc0_config3(cpu_env, arg);
rn = "Config3";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case 4:
/* currently ignored */
@@ -7470,7 +7466,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config5(cpu_env, arg);
rn = "Config5";
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
default:
@@ -7549,33 +7545,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
- /* BS_STOP isn't good enough here, hflags may have changed. */
+ /* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
rn = "Debug";
break;
case 1:
// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "TraceControl";
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "TraceControl2";
goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "UserTraceData";
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "TraceBPC";
goto cp0_unimplemented;
default:
@@ -7635,7 +7631,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
rn = "ErrCtl";
break;
default:
@@ -7728,10 +7724,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* For simplicity assume that all writes can cause interrupts. */
if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
gen_io_end();
- /* BS_STOP isn't sufficient, we need to ensure we break out of
+ /* DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
}
return;
@@ -8142,7 +8138,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
tcg_temp_free_i32(fs_tmp);
}
/* Stop translation as we may have changed hflags */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
/* COP2: Not implemented. */
case 4:
@@ -8301,7 +8297,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
check_insn(ctx, ISA_MIPS2);
gen_helper_eret(cpu_env);
}
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
}
break;
case OPC_DERET:
@@ -8316,7 +8312,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
generate_exception_end(ctx, EXCP_RI);
} else {
gen_helper_deret(cpu_env);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
}
break;
case OPC_WAIT:
@@ -8331,7 +8327,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
save_cpu_state(ctx, 1);
ctx->pc -= 4;
gen_helper_wait(cpu_env);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
break;
default:
die:
@@ -8756,7 +8752,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
tcg_temp_free_i32(fs_tmp);
}
/* Stop translation as we may have changed hflags */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
#if defined(TARGET_MIPS64)
case OPC_DMFC1:
@@ -10764,10 +10760,10 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
}
gen_store_gpr(t0, rt);
/* Break the TB to be able to take timer interrupts immediately
- after reading count. BS_STOP isn't sufficient, we need to ensure
+ after reading count. DISAS_STOP isn't sufficient, we need to ensure
we break completely out of translated code. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
break;
case 3:
gen_helper_rdhwr_ccres(t0, cpu_env);
@@ -10817,7 +10813,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
static inline void clear_branch_hflags(DisasContext *ctx)
{
ctx->hflags &= ~MIPS_HFLAG_BMASK;
- if (ctx->bstate == BS_NONE) {
+ if (ctx->is_jmp == DISAS_NEXT) {
save_cpu_state(ctx, 0);
} else {
/* it is not safe to save ctx->hflags as hflags may be changed
@@ -10832,7 +10828,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
/* Branches completion */
clear_branch_hflags(ctx);
- ctx->bstate = BS_BRANCH;
+ ctx->is_jmp = DISAS_NORETURN;
/* FIXME: Need to clear can_do_io. */
switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
case MIPS_HFLAG_FBNSLOT:
@@ -13574,7 +13570,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rs);
/* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
tcg_temp_free(t0);
}
break;
@@ -13586,10 +13582,10 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rs);
- /* BS_STOP isn't sufficient, we need to ensure we break out
+ /* DISAS_STOP isn't sufficient, we need to ensure we break out
of translated code to check for pending interrupts. */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
tcg_temp_free(t0);
}
break;
@@ -14745,7 +14741,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* SYNCI */
/* Break the TB to be able to sync copied instructions
immediately */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
} else {
/* TNEI */
mips32_op = OPC_TNEI;
@@ -14776,7 +14772,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Break the TB to be able to sync copied instructions
immediately */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case BC2F:
case BC2T:
@@ -19601,7 +19597,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, ISA_MIPS32R2);
/* Break the TB to be able to sync copied instructions
immediately */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)
@@ -19704,17 +19700,17 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched
the execution mode. */
- ctx->bstate = BS_STOP;
+ ctx->is_jmp = DISAS_STOP;
break;
case OPC_EI:
check_insn(ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt);
- /* BS_STOP isn't sufficient, we need to ensure we break out
- of translated code to check for pending interrupts. */
+ /* DISAS_STOP isn't sufficient, we need to ensure we break
+ out of translated code to check for pending interrupts */
gen_save_pc(ctx->pc + 4);
- ctx->bstate = BS_EXCP;
+ ctx->is_jmp = DISAS_EXCP;
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");
@@ -20216,7 +20212,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
ctx.insn_flags = env->insn_flags;
ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb;
- ctx.bstate = BS_NONE;
+ ctx.is_jmp = DISAS_NEXT;
ctx.btarget = 0;
ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
@@ -20257,13 +20253,13 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_tb_start(tb);
- while (ctx.bstate == BS_NONE) {
+ while (ctx.is_jmp == DISAS_NEXT) {
tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
save_cpu_state(&ctx, 1);
- ctx.bstate = BS_BRANCH;
+ ctx.is_jmp = DISAS_NORETURN;
gen_helper_raise_exception_debug(cpu_env);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
@@ -20337,22 +20333,22 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
- save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
+ if (cs->singlestep_enabled && ctx.is_jmp != DISAS_NORETURN) {
+ save_cpu_state(&ctx, ctx.is_jmp != DISAS_EXCP);
gen_helper_raise_exception_debug(cpu_env);
} else {
- switch (ctx.bstate) {
- case BS_STOP:
+ switch (ctx.is_jmp) {
+ case DISAS_STOP:
gen_goto_tb(&ctx, 0, ctx.pc);
break;
- case BS_NONE:
+ case DISAS_NEXT:
save_cpu_state(&ctx, 0);
gen_goto_tb(&ctx, 0, ctx.pc);
break;
- case BS_EXCP:
+ case DISAS_EXCP:
tcg_gen_exit_tb(0);
break;
- case BS_BRANCH:
+ case DISAS_NORETURN:
default:
break;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 06/14] target/mips: convert to DisasJumpType
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 06/14] target/mips: convert to DisasJumpType Emilio G. Cota
@ 2018-03-07 23:15 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 31+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-07 23:15 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel; +Cc: Yongbok Kim, Richard Henderson, Aurelien Jarno
On 03/01/2018 07:53 PM, Emilio G. Cota wrote:
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 186 +++++++++++++++++++++++-------------------------
> 1 file changed, 91 insertions(+), 95 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index d05ee67..a133205 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -36,6 +36,7 @@
>
> #include "target/mips/trace.h"
> #include "trace-tcg.h"
> +#include "exec/translator.h"
> #include "exec/log.h"
>
> #define MIPS_DEBUG_DISAS 0
> @@ -1439,7 +1440,7 @@ typedef struct DisasContext {
> int mem_idx;
> TCGMemOp default_tcg_memop_mask;
> uint32_t hflags, saved_hflags;
> - int bstate;
> + DisasJumpType is_jmp;
> target_ulong btarget;
> bool ulri;
> int kscrexist;
> @@ -1460,13 +1461,8 @@ typedef struct DisasContext {
> bool abs2008;
> } DisasContext;
>
> -enum {
> - BS_NONE = 0, /* We go out of the TB without reaching a branch or an
> - * exception condition */
> - BS_STOP = 1, /* We want to stop translation for any reason */
> - BS_BRANCH = 2, /* We reached a branch condition */
> - BS_EXCP = 3, /* We reached an exception condition */
> -};
> +#define DISAS_STOP DISAS_TARGET_0
> +#define DISAS_EXCP DISAS_TARGET_1
>
> static const char * const regnames[] = {
> "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
> @@ -1639,7 +1635,7 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
> gen_helper_raise_exception_err(cpu_env, texcp, terr);
> tcg_temp_free_i32(terr);
> tcg_temp_free_i32(texcp);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> }
>
> static inline void generate_exception(DisasContext *ctx, int excp)
> @@ -5334,10 +5330,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_io_end();
> }
> /* Break the TB to be able to take timer interrupts immediately
> - after reading count. BS_STOP isn't sufficient, we need to ensure
> - we break completely out of translated code. */
> + after reading count. DISAS_STOP isn't sufficient, we need to
> + ensure we break completely out of translated code. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Count";
> break;
> /* 6,7 are implementation dependent */
> @@ -5905,7 +5901,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_pagegrain(cpu_env, arg);
> rn = "PageGrain";
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 2:
> CP0_CHECK(ctx->sc);
> @@ -5966,7 +5962,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_hwrena(cpu_env, arg);
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "HWREna";
> break;
> default:
> @@ -6028,30 +6024,30 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> save_cpu_state(ctx, 1);
> gen_helper_mtc0_status(cpu_env, arg);
> - /* BS_STOP isn't good enough here, hflags may have changed. */
> + /* DISAS_STOP isn't good enough here, hflags may have changed. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Status";
> break;
> case 1:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_intctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "IntCtl";
> break;
> case 2:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_srsctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "SRSCtl";
> break;
> case 3:
> check_insn(ctx, ISA_MIPS32R2);
> gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "SRSMap";
> break;
> default:
> @@ -6063,11 +6059,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> save_cpu_state(ctx, 1);
> gen_helper_mtc0_cause(cpu_env, arg);
> - /* Stop translation as we may have triggered an interrupt. BS_STOP
> - * isn't sufficient, we need to ensure we break out of translated
> - * code to check for pending interrupts. */
> + /* Stop translation as we may have triggered an interrupt.
> + * DISAS_STOP isn't sufficient, we need to ensure we break out of
> + * translated code to check for pending interrupts. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Cause";
> break;
> default:
> @@ -6105,7 +6101,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config0(cpu_env, arg);
> rn = "Config";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 1:
> /* ignored, read only */
> @@ -6115,24 +6111,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config2(cpu_env, arg);
> rn = "Config2";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 3:
> gen_helper_mtc0_config3(cpu_env, arg);
> rn = "Config3";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 4:
> gen_helper_mtc0_config4(cpu_env, arg);
> rn = "Config4";
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 5:
> gen_helper_mtc0_config5(cpu_env, arg);
> rn = "Config5";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> /* 6,7 are implementation dependent */
> case 6:
> @@ -6221,35 +6217,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
> - /* BS_STOP isn't good enough here, hflags may have changed. */
> + /* DISAS_STOP isn't good enough here, hflags may have changed. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Debug";
> break;
> case 1:
> // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
> rn = "TraceControl";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
> rn = "TraceControl2";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> goto cp0_unimplemented;
> case 3:
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
> rn = "UserTraceData";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "TraceBPC";
> goto cp0_unimplemented;
> default:
> @@ -6309,7 +6305,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> gen_helper_mtc0_errctl(cpu_env, arg);
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "ErrCtl";
> break;
> default:
> @@ -6402,10 +6398,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* For simplicity assume that all writes can cause interrupts. */
> if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> gen_io_end();
> - /* BS_STOP isn't sufficient, we need to ensure we break out of
> + /* DISAS_STOP isn't sufficient, we need to ensure we break out of
> * translated code to check for pending interrupts. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> }
> return;
>
> @@ -6686,10 +6682,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_io_end();
> }
> /* Break the TB to be able to take timer interrupts immediately
> - after reading count. BS_STOP isn't sufficient, we need to ensure
> - we break completely out of translated code. */
> + after reading count. DISAS_STOP isn't sufficient, we need to
> + ensure we break completely out of translated code. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Count";
> break;
> /* 6,7 are implementation dependent */
> @@ -7301,7 +7297,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_hwrena(cpu_env, arg);
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "HWREna";
> break;
> default:
> @@ -7337,7 +7333,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> goto cp0_unimplemented;
> }
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 10:
> switch (sel) {
> @@ -7360,37 +7356,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> goto cp0_unimplemented;
> }
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 12:
> switch (sel) {
> case 0:
> save_cpu_state(ctx, 1);
> gen_helper_mtc0_status(cpu_env, arg);
> - /* BS_STOP isn't good enough here, hflags may have changed. */
> + /* DISAS_STOP isn't good enough here, hflags may have changed. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Status";
> break;
> case 1:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_intctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "IntCtl";
> break;
> case 2:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_srsctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "SRSCtl";
> break;
> case 3:
> check_insn(ctx, ISA_MIPS32R2);
> gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "SRSMap";
> break;
> default:
> @@ -7402,11 +7398,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> save_cpu_state(ctx, 1);
> gen_helper_mtc0_cause(cpu_env, arg);
> - /* Stop translation as we may have triggered an intetrupt. BS_STOP
> - * isn't sufficient, we need to ensure we break out of translated
> - * code to check for pending interrupts. */
> + /* Stop translation as we may have triggered an intetrupt.
> + * DISAS_STOP isn't sufficient, we need to ensure we break out of
> + * translated code to check for pending interrupts. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Cause";
> break;
> default:
> @@ -7444,7 +7440,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config0(cpu_env, arg);
> rn = "Config";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 1:
> /* ignored, read only */
> @@ -7454,13 +7450,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config2(cpu_env, arg);
> rn = "Config2";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 3:
> gen_helper_mtc0_config3(cpu_env, arg);
> rn = "Config3";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case 4:
> /* currently ignored */
> @@ -7470,7 +7466,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config5(cpu_env, arg);
> rn = "Config5";
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> /* 6,7 are implementation dependent */
> default:
> @@ -7549,33 +7545,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
> - /* BS_STOP isn't good enough here, hflags may have changed. */
> + /* DISAS_STOP isn't good enough here, hflags may have changed. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> rn = "Debug";
> break;
> case 1:
> // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "TraceControl";
> goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "TraceControl2";
> goto cp0_unimplemented;
> case 3:
> // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "UserTraceData";
> goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "TraceBPC";
> goto cp0_unimplemented;
> default:
> @@ -7635,7 +7631,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> gen_helper_mtc0_errctl(cpu_env, arg);
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> rn = "ErrCtl";
> break;
> default:
> @@ -7728,10 +7724,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* For simplicity assume that all writes can cause interrupts. */
> if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> gen_io_end();
> - /* BS_STOP isn't sufficient, we need to ensure we break out of
> + /* DISAS_STOP isn't sufficient, we need to ensure we break out of
> * translated code to check for pending interrupts. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> }
> return;
>
> @@ -8142,7 +8138,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
> tcg_temp_free_i32(fs_tmp);
> }
> /* Stop translation as we may have changed hflags */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> /* COP2: Not implemented. */
> case 4:
> @@ -8301,7 +8297,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
> check_insn(ctx, ISA_MIPS2);
> gen_helper_eret(cpu_env);
> }
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> }
> break;
> case OPC_DERET:
> @@ -8316,7 +8312,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
> generate_exception_end(ctx, EXCP_RI);
> } else {
> gen_helper_deret(cpu_env);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> }
> break;
> case OPC_WAIT:
> @@ -8331,7 +8327,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
> save_cpu_state(ctx, 1);
> ctx->pc -= 4;
> gen_helper_wait(cpu_env);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> break;
> default:
> die:
> @@ -8756,7 +8752,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
> tcg_temp_free_i32(fs_tmp);
> }
> /* Stop translation as we may have changed hflags */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> #if defined(TARGET_MIPS64)
> case OPC_DMFC1:
> @@ -10764,10 +10760,10 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
> }
> gen_store_gpr(t0, rt);
> /* Break the TB to be able to take timer interrupts immediately
> - after reading count. BS_STOP isn't sufficient, we need to ensure
> + after reading count. DISAS_STOP isn't sufficient, we need to ensure
> we break completely out of translated code. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> break;
> case 3:
> gen_helper_rdhwr_ccres(t0, cpu_env);
> @@ -10817,7 +10813,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
> static inline void clear_branch_hflags(DisasContext *ctx)
> {
> ctx->hflags &= ~MIPS_HFLAG_BMASK;
> - if (ctx->bstate == BS_NONE) {
> + if (ctx->is_jmp == DISAS_NEXT) {
> save_cpu_state(ctx, 0);
> } else {
> /* it is not safe to save ctx->hflags as hflags may be changed
> @@ -10832,7 +10828,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
> int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
> /* Branches completion */
> clear_branch_hflags(ctx);
> - ctx->bstate = BS_BRANCH;
> + ctx->is_jmp = DISAS_NORETURN;
> /* FIXME: Need to clear can_do_io. */
> switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
> case MIPS_HFLAG_FBNSLOT:
> @@ -13574,7 +13570,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
> gen_helper_di(t0, cpu_env);
> gen_store_gpr(t0, rs);
> /* Stop translation as we may have switched the execution mode */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> tcg_temp_free(t0);
> }
> break;
> @@ -13586,10 +13582,10 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
> save_cpu_state(ctx, 1);
> gen_helper_ei(t0, cpu_env);
> gen_store_gpr(t0, rs);
> - /* BS_STOP isn't sufficient, we need to ensure we break out
> + /* DISAS_STOP isn't sufficient, we need to ensure we break out
> of translated code to check for pending interrupts. */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> tcg_temp_free(t0);
> }
> break;
> @@ -14745,7 +14741,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
> /* SYNCI */
> /* Break the TB to be able to sync copied instructions
> immediately */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> } else {
> /* TNEI */
> mips32_op = OPC_TNEI;
> @@ -14776,7 +14772,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> /* Break the TB to be able to sync copied instructions
> immediately */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case BC2F:
> case BC2T:
> @@ -19601,7 +19597,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> check_insn(ctx, ISA_MIPS32R2);
> /* Break the TB to be able to sync copied instructions
> immediately */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case OPC_BPOSGE32: /* MIPS DSP branch */
> #if defined(TARGET_MIPS64)
> @@ -19704,17 +19700,17 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> gen_store_gpr(t0, rt);
> /* Stop translation as we may have switched
> the execution mode. */
> - ctx->bstate = BS_STOP;
> + ctx->is_jmp = DISAS_STOP;
> break;
> case OPC_EI:
> check_insn(ctx, ISA_MIPS32R2);
> save_cpu_state(ctx, 1);
> gen_helper_ei(t0, cpu_env);
> gen_store_gpr(t0, rt);
> - /* BS_STOP isn't sufficient, we need to ensure we break out
> - of translated code to check for pending interrupts. */
> + /* DISAS_STOP isn't sufficient, we need to ensure we break
> + out of translated code to check for pending interrupts */
> gen_save_pc(ctx->pc + 4);
> - ctx->bstate = BS_EXCP;
> + ctx->is_jmp = DISAS_EXCP;
> break;
> default: /* Invalid */
> MIPS_INVAL("mfmc0");
> @@ -20216,7 +20212,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> ctx.insn_flags = env->insn_flags;
> ctx.CP0_Config1 = env->CP0_Config1;
> ctx.tb = tb;
> - ctx.bstate = BS_NONE;
> + ctx.is_jmp = DISAS_NEXT;
> ctx.btarget = 0;
> ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
> @@ -20257,13 +20253,13 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
>
> LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
> gen_tb_start(tb);
> - while (ctx.bstate == BS_NONE) {
> + while (ctx.is_jmp == DISAS_NEXT) {
> tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
> num_insns++;
>
> if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
> save_cpu_state(&ctx, 1);
> - ctx.bstate = BS_BRANCH;
> + ctx.is_jmp = DISAS_NORETURN;
> gen_helper_raise_exception_debug(cpu_env);
> /* The address covered by the breakpoint must be included in
> [tb->pc, tb->pc + tb->size) in order to for it to be
> @@ -20337,22 +20333,22 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> if (tb_cflags(tb) & CF_LAST_IO) {
> gen_io_end();
> }
> - if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
> - save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
> + if (cs->singlestep_enabled && ctx.is_jmp != DISAS_NORETURN) {
> + save_cpu_state(&ctx, ctx.is_jmp != DISAS_EXCP);
> gen_helper_raise_exception_debug(cpu_env);
> } else {
> - switch (ctx.bstate) {
> - case BS_STOP:
> + switch (ctx.is_jmp) {
> + case DISAS_STOP:
> gen_goto_tb(&ctx, 0, ctx.pc);
> break;
> - case BS_NONE:
> + case DISAS_NEXT:
> save_cpu_state(&ctx, 0);
> gen_goto_tb(&ctx, 0, ctx.pc);
> break;
> - case BS_EXCP:
> + case DISAS_EXCP:
> tcg_gen_exit_tb(0);
> break;
> - case BS_BRANCH:
> + case DISAS_NORETURN:
> default:
> break;
> }
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Qemu-devel] [PATCHv1 07/14] target/mips: convert to DisasContextBase
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (5 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 06/14] target/mips: convert to DisasJumpType Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-07 23:21 ` Philippe Mathieu-Daudé
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext Emilio G. Cota
` (10 subsequent siblings)
17 siblings, 1 reply; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno, Yongbok Kim
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/mips/translate.c | 346 ++++++++++++++++++++++++------------------------
1 file changed, 175 insertions(+), 171 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a133205..aefd729 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1430,17 +1430,15 @@ static TCGv_i64 msa_wr_d[64];
} while(0)
typedef struct DisasContext {
- struct TranslationBlock *tb;
- target_ulong pc, saved_pc;
+ DisasContextBase base;
+ target_ulong saved_pc;
uint32_t opcode;
- int singlestep_enabled;
int insn_flags;
int32_t CP0_Config1;
/* Routine used to access memory */
int mem_idx;
TCGMemOp default_tcg_memop_mask;
uint32_t hflags, saved_hflags;
- DisasJumpType is_jmp;
target_ulong btarget;
bool ulri;
int kscrexist;
@@ -1517,8 +1515,9 @@ static const char * const msaregnames[] = {
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, \
TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
- ctx->pc, ctx->opcode, op, ctx->opcode >> 26, \
- ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
+ ctx->base.pc_next, ctx->opcode, op, \
+ ctx->opcode >> 26, ctx->opcode & 0x3F, \
+ ((ctx->opcode >> 16) & 0x1F)); \
} \
} while (0)
@@ -1594,9 +1593,9 @@ static inline void gen_save_pc(target_ulong pc)
static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
{
LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
- if (do_save_pc && ctx->pc != ctx->saved_pc) {
- gen_save_pc(ctx->pc);
- ctx->saved_pc = ctx->pc;
+ if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) {
+ gen_save_pc(ctx->base.pc_next);
+ ctx->saved_pc = ctx->base.pc_next;
}
if (ctx->hflags != ctx->saved_hflags) {
tcg_gen_movi_i32(hflags, ctx->hflags);
@@ -1635,7 +1634,7 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
gen_helper_raise_exception_err(cpu_env, texcp, terr);
tcg_temp_free_i32(terr);
tcg_temp_free_i32(texcp);
- ctx->is_jmp = DISAS_EXCP;
+ ctx->base.is_jmp = DISAS_EXCP;
}
static inline void generate_exception(DisasContext *ctx, int excp)
@@ -2126,7 +2125,7 @@ static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
static target_ulong pc_relative_pc (DisasContext *ctx)
{
- target_ulong pc = ctx->pc;
+ target_ulong pc = ctx->base.pc_next;
if (ctx->hflags & MIPS_HFLAG_BMASK) {
int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
@@ -4275,12 +4274,12 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
- if (unlikely(ctx->singlestep_enabled)) {
+ if (unlikely(ctx->base.singlestep_enabled)) {
return false;
}
#ifndef CONFIG_USER_ONLY
- return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+ return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
@@ -4291,10 +4290,10 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
if (use_goto_tb(ctx, dest)) {
tcg_gen_goto_tb(n);
gen_save_pc(dest);
- tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n);
} else {
gen_save_pc(dest);
- if (ctx->singlestep_enabled) {
+ if (ctx->base.singlestep_enabled) {
save_cpu_state(ctx, 0);
gen_helper_raise_exception_debug(cpu_env);
}
@@ -4317,7 +4316,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
- TARGET_FMT_lx "\n", ctx->pc);
+ TARGET_FMT_lx "\n", ctx->base.pc_next);
#endif
generate_exception_end(ctx, EXCP_RI);
goto out;
@@ -4335,7 +4334,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
bcond_compute = 1;
}
- btgt = ctx->pc + insn_bytes + offset;
+ btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_BGEZ:
case OPC_BGEZAL:
@@ -4354,7 +4353,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rs);
bcond_compute = 1;
}
- btgt = ctx->pc + insn_bytes + offset;
+ btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_BPOSGE32:
#if defined(TARGET_MIPS64)
@@ -4364,13 +4363,14 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
#endif
bcond_compute = 1;
- btgt = ctx->pc + insn_bytes + offset;
+ btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_J:
case OPC_JAL:
case OPC_JALX:
/* Jump to immediate */
- btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset;
+ btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
+ (uint32_t)offset;
break;
case OPC_JR:
case OPC_JALR:
@@ -4416,19 +4416,19 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
/* Handle as an unconditional branch to get correct delay
slot checking. */
blink = 31;
- btgt = ctx->pc + insn_bytes + delayslot_size;
+ btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
ctx->hflags |= MIPS_HFLAG_B;
break;
case OPC_BLTZALL: /* 0 < 0 likely */
- tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
+ tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
/* Skip the instruction in the delay slot */
- ctx->pc += 4;
+ ctx->base.pc_next += 4;
goto out;
case OPC_BNEL: /* rx != rx likely */
case OPC_BGTZL: /* 0 > 0 likely */
case OPC_BLTZL: /* 0 < 0 likely */
/* Skip the instruction in the delay slot */
- ctx->pc += 4;
+ ctx->base.pc_next += 4;
goto out;
case OPC_J:
ctx->hflags |= MIPS_HFLAG_B;
@@ -4540,7 +4540,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
int post_delay = insn_bytes + delayslot_size;
int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
- tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit);
+ tcg_gen_movi_tl(cpu_gpr[blink],
+ ctx->base.pc_next + post_delay + lowbit);
}
out:
@@ -5322,18 +5323,18 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_mfc0_count(arg, cpu_env);
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
/* Break the TB to be able to take timer interrupts immediately
after reading count. DISAS_STOP isn't sufficient, we need to
ensure we break completely out of translated code. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -5729,7 +5730,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
if (sel != 0)
check_insn(ctx, ISA_MIPS32);
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
@@ -5901,7 +5902,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
rn = "PageGrain";
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 2:
CP0_CHECK(ctx->sc);
@@ -5962,7 +5963,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "HWREna";
break;
default:
@@ -6025,29 +6026,29 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "SRSMap";
break;
default:
@@ -6062,8 +6063,8 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Cause";
break;
default:
@@ -6101,7 +6102,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config0(cpu_env, arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 1:
/* ignored, read only */
@@ -6111,24 +6112,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config2(cpu_env, arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 3:
gen_helper_mtc0_config3(cpu_env, arg);
rn = "Config3";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 4:
gen_helper_mtc0_config4(cpu_env, arg);
rn = "Config4";
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 5:
gen_helper_mtc0_config5(cpu_env, arg);
rn = "Config5";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
case 6:
@@ -6218,34 +6219,34 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Debug";
break;
case 1:
// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 3:
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "TraceBPC";
goto cp0_unimplemented;
default:
@@ -6305,7 +6306,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "ErrCtl";
break;
default:
@@ -6396,12 +6397,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
trace_mips_translate_c0("mtc0", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
/* DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
}
return;
@@ -6674,18 +6675,18 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* Mark as an IO operation because we read the time. */
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_mfc0_count(arg, cpu_env);
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
/* Break the TB to be able to take timer interrupts immediately
after reading count. DISAS_STOP isn't sufficient, we need to
ensure we break completely out of translated code. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -7067,7 +7068,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
if (sel != 0)
check_insn(ctx, ISA_MIPS64);
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
@@ -7297,7 +7298,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "HWREna";
break;
default:
@@ -7333,7 +7334,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 10:
switch (sel) {
@@ -7356,7 +7357,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 12:
switch (sel) {
@@ -7364,29 +7365,29 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Status";
break;
case 1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "SRSCtl";
break;
case 3:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "SRSMap";
break;
default:
@@ -7401,8 +7402,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have triggered an intetrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Cause";
break;
default:
@@ -7440,7 +7441,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config0(cpu_env, arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 1:
/* ignored, read only */
@@ -7450,13 +7451,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config2(cpu_env, arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 3:
gen_helper_mtc0_config3(cpu_env, arg);
rn = "Config3";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case 4:
/* currently ignored */
@@ -7466,7 +7467,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_config5(cpu_env, arg);
rn = "Config5";
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
default:
@@ -7546,32 +7547,32 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 0:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
rn = "Debug";
break;
case 1:
// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "TraceControl";
goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "TraceControl2";
goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "UserTraceData";
goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "TraceBPC";
goto cp0_unimplemented;
default:
@@ -7631,7 +7632,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
gen_helper_mtc0_errctl(cpu_env, arg);
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
rn = "ErrCtl";
break;
default:
@@ -7722,12 +7723,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
trace_mips_translate_c0("dmtc0", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
/* DISAS_STOP isn't sufficient, we need to ensure we break out of
* translated code to check for pending interrupts. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
}
return;
@@ -8138,7 +8139,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
tcg_temp_free_i32(fs_tmp);
}
/* Stop translation as we may have changed hflags */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
/* COP2: Not implemented. */
case 4:
@@ -8297,7 +8298,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
check_insn(ctx, ISA_MIPS2);
gen_helper_eret(cpu_env);
}
- ctx->is_jmp = DISAS_EXCP;
+ ctx->base.is_jmp = DISAS_EXCP;
}
break;
case OPC_DERET:
@@ -8312,7 +8313,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
generate_exception_end(ctx, EXCP_RI);
} else {
gen_helper_deret(cpu_env);
- ctx->is_jmp = DISAS_EXCP;
+ ctx->base.is_jmp = DISAS_EXCP;
}
break;
case OPC_WAIT:
@@ -8323,11 +8324,11 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
goto die;
}
/* If we get an exception, we want to restart at next instruction */
- ctx->pc += 4;
+ ctx->base.pc_next += 4;
save_cpu_state(ctx, 1);
- ctx->pc -= 4;
+ ctx->base.pc_next -= 4;
gen_helper_wait(cpu_env);
- ctx->is_jmp = DISAS_EXCP;
+ ctx->base.is_jmp = DISAS_EXCP;
break;
default:
die:
@@ -8354,7 +8355,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
if (cc != 0)
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
- btarget = ctx->pc + 4 + offset;
+ btarget = ctx->base.pc_next + 4 + offset;
switch (op) {
case OPC_BC1F:
@@ -8457,7 +8458,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
- "\n", ctx->pc);
+ "\n", ctx->base.pc_next);
#endif
generate_exception_end(ctx, EXCP_RI);
goto out;
@@ -8466,7 +8467,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
gen_load_fpr64(ctx, t0, ft);
tcg_gen_andi_i64(t0, t0, 1);
- btarget = addr_add(ctx, ctx->pc + 4, offset);
+ btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
switch (op) {
case OPC_BC1EQZ:
@@ -8752,7 +8753,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
tcg_temp_free_i32(fs_tmp);
}
/* Stop translation as we may have changed hflags */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
#if defined(TARGET_MIPS64)
case OPC_DMFC1:
@@ -10751,19 +10752,19 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 2:
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_rdhwr_cc(t0, cpu_env);
- if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
gen_store_gpr(t0, rt);
/* Break the TB to be able to take timer interrupts immediately
after reading count. DISAS_STOP isn't sufficient, we need to ensure
we break completely out of translated code. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
break;
case 3:
gen_helper_rdhwr_ccres(t0, cpu_env);
@@ -10813,7 +10814,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
static inline void clear_branch_hflags(DisasContext *ctx)
{
ctx->hflags &= ~MIPS_HFLAG_BMASK;
- if (ctx->is_jmp == DISAS_NEXT) {
+ if (ctx->base.is_jmp == DISAS_NEXT) {
save_cpu_state(ctx, 0);
} else {
/* it is not safe to save ctx->hflags as hflags may be changed
@@ -10828,11 +10829,11 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
/* Branches completion */
clear_branch_hflags(ctx);
- ctx->is_jmp = DISAS_NORETURN;
+ ctx->base.is_jmp = DISAS_NORETURN;
/* FIXME: Need to clear can_do_io. */
switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
case MIPS_HFLAG_FBNSLOT:
- gen_goto_tb(ctx, 0, ctx->pc + insn_bytes);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes);
break;
case MIPS_HFLAG_B:
/* unconditional branch */
@@ -10851,7 +10852,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
TCGLabel *l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
- gen_goto_tb(ctx, 1, ctx->pc + insn_bytes);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes);
gen_set_label(l1);
gen_goto_tb(ctx, 0, ctx->btarget);
}
@@ -10874,7 +10875,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
} else {
tcg_gen_mov_tl(cpu_PC, btarget);
}
- if (ctx->singlestep_enabled) {
+ if (ctx->base.singlestep_enabled) {
save_cpu_state(ctx, 0);
gen_helper_raise_exception_debug(cpu_env);
}
@@ -10899,7 +10900,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
- "\n", ctx->pc);
+ "\n", ctx->base.pc_next);
#endif
generate_exception_end(ctx, EXCP_RI);
goto out;
@@ -10913,10 +10914,10 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
- ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
if (rs <= rt && rs == 0) {
/* OPC_BEQZALC, OPC_BNEZALC */
- tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
+ tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
}
break;
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
@@ -10924,23 +10925,23 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
- ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
break;
case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
if (rs == 0 || rs == rt) {
/* OPC_BLEZALC, OPC_BGEZALC */
/* OPC_BGTZALC, OPC_BLTZALC */
- tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
+ tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
}
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
bcond_compute = 1;
- ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
break;
case OPC_BC:
case OPC_BALC:
- ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
break;
case OPC_BEQZC:
case OPC_BNEZC:
@@ -10948,7 +10949,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
/* OPC_BEQZC, OPC_BNEZC */
gen_load_gpr(t0, rs);
bcond_compute = 1;
- ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
@@ -10971,13 +10972,13 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
/* Uncoditional compact branch */
switch (opc) {
case OPC_JIALC:
- tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
+ tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
/* Fallthrough */
case OPC_JIC:
ctx->hflags |= MIPS_HFLAG_BR;
break;
case OPC_BALC:
- tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
+ tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
/* Fallthrough */
case OPC_BC:
ctx->hflags |= MIPS_HFLAG_B;
@@ -11602,7 +11603,7 @@ static void decode_i64_mips16 (DisasContext *ctx,
static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
{
- int extend = cpu_lduw_code(env, ctx->pc + 2);
+ int extend = cpu_lduw_code(env, ctx->base.pc_next + 2);
int op, rx, ry, funct, sa;
int16_t imm, offset;
@@ -11842,7 +11843,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
/* No delay slot, so just process as a normal instruction */
break;
case M16_OPC_JAL:
- offset = cpu_lduw_code(env, ctx->pc + 2);
+ offset = cpu_lduw_code(env, ctx->base.pc_next + 2);
offset = (((ctx->opcode & 0x1f) << 21)
| ((ctx->opcode >> 5) & 0x1f) << 16
| offset) << 2;
@@ -13570,7 +13571,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rs);
/* Stop translation as we may have switched the execution mode */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
tcg_temp_free(t0);
}
break;
@@ -13584,8 +13585,8 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_store_gpr(t0, rs);
/* DISAS_STOP isn't sufficient, we need to ensure we break out
of translated code to check for pending interrupts. */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
tcg_temp_free(t0);
}
break;
@@ -13940,7 +13941,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
uint32_t op, minor, minor2, mips32_op;
uint32_t cond, fmt, cc;
- insn = cpu_lduw_code(env, ctx->pc + 2);
+ insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
ctx->opcode = (ctx->opcode << 16) | insn;
rt = (ctx->opcode >> 21) & 0x1f;
@@ -14741,7 +14742,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* SYNCI */
/* Break the TB to be able to sync copied instructions
immediately */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
} else {
/* TNEI */
mips32_op = OPC_TNEI;
@@ -14772,7 +14773,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Break the TB to be able to sync copied instructions
immediately */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case BC2F:
case BC2T:
@@ -15135,16 +15136,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
switch ((ctx->opcode >> 16) & 0x1f) {
case ADDIUPC_00 ... ADDIUPC_07:
- gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
+ gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt);
break;
case AUIPC:
- gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
+ gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt);
break;
case ALUIPC:
- gen_pcrel(ctx, OPC_ALUIPC, ctx->pc, rt);
+ gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt);
break;
case LWPC_08 ... LWPC_0F:
- gen_pcrel(ctx, R6_OPC_LWPC, ctx->pc & ~0x3, rt);
+ gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt);
break;
default:
generate_exception(ctx, EXCP_RI);
@@ -15276,8 +15277,8 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
uint32_t op;
/* make sure instructions are on a halfword boundary */
- if (ctx->pc & 0x1) {
- env->CP0_BadVAddr = ctx->pc;
+ if (ctx->base.pc_next & 0x1) {
+ env->CP0_BadVAddr = ctx->base.pc_next;
generate_exception_end(ctx, EXCP_AdEL);
return 2;
}
@@ -18503,7 +18504,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
break;
}
- ctx->btarget = ctx->pc + (s16 << 2) + 4;
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
@@ -19524,8 +19525,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
int16_t imm;
/* make sure instructions are on a word boundary */
- if (ctx->pc & 0x3) {
- env->CP0_BadVAddr = ctx->pc;
+ if (ctx->base.pc_next & 0x3) {
+ env->CP0_BadVAddr = ctx->base.pc_next;
generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
return;
}
@@ -19536,7 +19537,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
- gen_goto_tb(ctx, 1, ctx->pc + 4);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
gen_set_label(l1);
}
@@ -19597,7 +19598,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, ISA_MIPS32R2);
/* Break the TB to be able to sync copied instructions
immediately */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)
@@ -19700,7 +19701,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched
the execution mode. */
- ctx->is_jmp = DISAS_STOP;
+ ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_EI:
check_insn(ctx, ISA_MIPS32R2);
@@ -19709,8 +19710,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
/* DISAS_STOP isn't sufficient, we need to ensure we break
out of translated code to check for pending interrupts */
- gen_save_pc(ctx->pc + 4);
- ctx->is_jmp = DISAS_EXCP;
+ gen_save_pc(ctx->base.pc_next + 4);
+ ctx->base.is_jmp = DISAS_EXCP;
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");
@@ -20184,7 +20185,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS32R6);
- gen_pcrel(ctx, ctx->opcode, ctx->pc, rs);
+ gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
@@ -20197,22 +20198,22 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUMIPSState *env = cs->env_ptr;
DisasContext ctx;
- target_ulong pc_start;
target_ulong next_page_start;
- int num_insns;
int max_insns;
int insn_bytes;
int is_slot;
- pc_start = tb->pc;
- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- ctx.pc = pc_start;
+ ctx.base.tb = tb;
+ ctx.base.pc_first = tb->pc;
+ ctx.base.pc_next = tb->pc;
+ ctx.base.is_jmp = DISAS_NEXT;
+ ctx.base.singlestep_enabled = cs->singlestep_enabled;
+ ctx.base.num_insns = 0;
+
+ next_page_start = (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
ctx.saved_pc = -1;
- ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.insn_flags = env->insn_flags;
ctx.CP0_Config1 = env->CP0_Config1;
- ctx.tb = tb;
- ctx.is_jmp = DISAS_NEXT;
ctx.btarget = 0;
ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
@@ -20226,7 +20227,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
/* Restore delay slot state from the tb context. */
- ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
+ ctx.hflags = (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bits? */
ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
@@ -20242,7 +20243,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
#endif
ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
MO_UNALN : MO_ALIGN;
- num_insns = 0;
max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
@@ -20253,36 +20253,37 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_tb_start(tb);
- while (ctx.is_jmp == DISAS_NEXT) {
- tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
- num_insns++;
+ while (ctx.base.is_jmp == DISAS_NEXT) {
+ tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK,
+ ctx.btarget);
+ ctx.base.num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
save_cpu_state(&ctx, 1);
- ctx.is_jmp = DISAS_NORETURN;
+ ctx.base.is_jmp = DISAS_NORETURN;
gen_helper_raise_exception_debug(cpu_env);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
- ctx.pc += 4;
+ ctx.base.pc_next += 4;
goto done_generating;
}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
+ if (ctx.base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
if (!(ctx.hflags & MIPS_HFLAG_M16)) {
- ctx.opcode = cpu_ldl_code(env, ctx.pc);
+ ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next);
insn_bytes = 4;
decode_opc(env, &ctx);
} else if (ctx.insn_flags & ASE_MICROMIPS) {
- ctx.opcode = cpu_lduw_code(env, ctx.pc);
+ ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
insn_bytes = decode_micromips_opc(env, &ctx);
} else if (ctx.insn_flags & ASE_MIPS16) {
- ctx.opcode = cpu_lduw_code(env, ctx.pc);
+ ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
insn_bytes = decode_mips16_opc(env, &ctx);
} else {
generate_exception_end(&ctx, EXCP_RI);
@@ -20306,17 +20307,18 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (is_slot) {
gen_branch(&ctx, insn_bytes);
}
- ctx.pc += insn_bytes;
+ ctx.base.pc_next += insn_bytes;
/* Execute a branch and its delay slot as a single instruction.
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
+ if (ctx.base.singlestep_enabled &&
+ (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
break;
}
- if (ctx.pc >= next_page_start) {
+ if (ctx.base.pc_next >= next_page_start) {
break;
}
@@ -20324,8 +20326,9 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
break;
}
- if (num_insns >= max_insns)
+ if (ctx.base.num_insns >= max_insns) {
break;
+ }
if (singlestep)
break;
@@ -20333,17 +20336,17 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (cs->singlestep_enabled && ctx.is_jmp != DISAS_NORETURN) {
- save_cpu_state(&ctx, ctx.is_jmp != DISAS_EXCP);
+ if (ctx.base.singlestep_enabled && ctx.base.is_jmp != DISAS_NORETURN) {
+ save_cpu_state(&ctx, ctx.base.is_jmp != DISAS_EXCP);
gen_helper_raise_exception_debug(cpu_env);
} else {
- switch (ctx.is_jmp) {
+ switch (ctx.base.is_jmp) {
case DISAS_STOP:
- gen_goto_tb(&ctx, 0, ctx.pc);
+ gen_goto_tb(&ctx, 0, ctx.base.pc_next);
break;
case DISAS_NEXT:
save_cpu_state(&ctx, 0);
- gen_goto_tb(&ctx, 0, ctx.pc);
+ gen_goto_tb(&ctx, 0, ctx.base.pc_next);
break;
case DISAS_EXCP:
tcg_gen_exit_tb(0);
@@ -20354,18 +20357,19 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
}
}
done_generating:
- gen_tb_end(tb, num_insns);
+ gen_tb_end(tb, ctx.base.num_insns);
- tb->size = ctx.pc - pc_start;
- tb->icount = num_insns;
+ tb->size = ctx.base.pc_next - ctx.base.pc_first;
+ tb->icount = ctx.base.num_insns;
#ifdef DEBUG_DISAS
LOG_DISAS("\n");
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
+ && qemu_log_in_addr_range(ctx.base.pc_first)) {
qemu_log_lock();
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, ctx.pc - pc_start);
+ qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first));
+ log_target_disas(cs, ctx.base.pc_first,
+ ctx.base.pc_next - ctx.base.pc_first);
qemu_log("\n");
qemu_log_unlock();
}
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 07/14] target/mips: convert to DisasContextBase
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 07/14] target/mips: convert to DisasContextBase Emilio G. Cota
@ 2018-03-07 23:21 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 31+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-07 23:21 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel; +Cc: Yongbok Kim, Richard Henderson, Aurelien Jarno
On 03/01/2018 07:53 PM, Emilio G. Cota wrote:
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 346 ++++++++++++++++++++++++------------------------
> 1 file changed, 175 insertions(+), 171 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index a133205..aefd729 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1430,17 +1430,15 @@ static TCGv_i64 msa_wr_d[64];
> } while(0)
>
> typedef struct DisasContext {
> - struct TranslationBlock *tb;
> - target_ulong pc, saved_pc;
> + DisasContextBase base;
> + target_ulong saved_pc;
> uint32_t opcode;
> - int singlestep_enabled;
> int insn_flags;
> int32_t CP0_Config1;
> /* Routine used to access memory */
> int mem_idx;
> TCGMemOp default_tcg_memop_mask;
> uint32_t hflags, saved_hflags;
> - DisasJumpType is_jmp;
> target_ulong btarget;
> bool ulri;
> int kscrexist;
> @@ -1517,8 +1515,9 @@ static const char * const msaregnames[] = {
> if (MIPS_DEBUG_DISAS) { \
> qemu_log_mask(CPU_LOG_TB_IN_ASM, \
> TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
> - ctx->pc, ctx->opcode, op, ctx->opcode >> 26, \
> - ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
> + ctx->base.pc_next, ctx->opcode, op, \
> + ctx->opcode >> 26, ctx->opcode & 0x3F, \
> + ((ctx->opcode >> 16) & 0x1F)); \
> } \
> } while (0)
>
> @@ -1594,9 +1593,9 @@ static inline void gen_save_pc(target_ulong pc)
> static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
> {
> LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
> - if (do_save_pc && ctx->pc != ctx->saved_pc) {
> - gen_save_pc(ctx->pc);
> - ctx->saved_pc = ctx->pc;
> + if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) {
> + gen_save_pc(ctx->base.pc_next);
> + ctx->saved_pc = ctx->base.pc_next;
> }
> if (ctx->hflags != ctx->saved_hflags) {
> tcg_gen_movi_i32(hflags, ctx->hflags);
> @@ -1635,7 +1634,7 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
> gen_helper_raise_exception_err(cpu_env, texcp, terr);
> tcg_temp_free_i32(terr);
> tcg_temp_free_i32(texcp);
> - ctx->is_jmp = DISAS_EXCP;
> + ctx->base.is_jmp = DISAS_EXCP;
> }
>
> static inline void generate_exception(DisasContext *ctx, int excp)
> @@ -2126,7 +2125,7 @@ static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
>
> static target_ulong pc_relative_pc (DisasContext *ctx)
> {
> - target_ulong pc = ctx->pc;
> + target_ulong pc = ctx->base.pc_next;
>
> if (ctx->hflags & MIPS_HFLAG_BMASK) {
> int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
> @@ -4275,12 +4274,12 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
>
> static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
> {
> - if (unlikely(ctx->singlestep_enabled)) {
> + if (unlikely(ctx->base.singlestep_enabled)) {
> return false;
> }
>
> #ifndef CONFIG_USER_ONLY
> - return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
> + return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
> #else
> return true;
> #endif
> @@ -4291,10 +4290,10 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> if (use_goto_tb(ctx, dest)) {
> tcg_gen_goto_tb(n);
> gen_save_pc(dest);
> - tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
> + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n);
> } else {
> gen_save_pc(dest);
> - if (ctx->singlestep_enabled) {
> + if (ctx->base.singlestep_enabled) {
> save_cpu_state(ctx, 0);
> gen_helper_raise_exception_debug(cpu_env);
> }
> @@ -4317,7 +4316,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> if (ctx->hflags & MIPS_HFLAG_BMASK) {
> #ifdef MIPS_DEBUG_DISAS
> LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
> - TARGET_FMT_lx "\n", ctx->pc);
> + TARGET_FMT_lx "\n", ctx->base.pc_next);
> #endif
> generate_exception_end(ctx, EXCP_RI);
> goto out;
> @@ -4335,7 +4334,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> gen_load_gpr(t1, rt);
> bcond_compute = 1;
> }
> - btgt = ctx->pc + insn_bytes + offset;
> + btgt = ctx->base.pc_next + insn_bytes + offset;
> break;
> case OPC_BGEZ:
> case OPC_BGEZAL:
> @@ -4354,7 +4353,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> gen_load_gpr(t0, rs);
> bcond_compute = 1;
> }
> - btgt = ctx->pc + insn_bytes + offset;
> + btgt = ctx->base.pc_next + insn_bytes + offset;
> break;
> case OPC_BPOSGE32:
> #if defined(TARGET_MIPS64)
> @@ -4364,13 +4363,14 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
> #endif
> bcond_compute = 1;
> - btgt = ctx->pc + insn_bytes + offset;
> + btgt = ctx->base.pc_next + insn_bytes + offset;
> break;
> case OPC_J:
> case OPC_JAL:
> case OPC_JALX:
> /* Jump to immediate */
> - btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset;
> + btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
> + (uint32_t)offset;
> break;
> case OPC_JR:
> case OPC_JALR:
> @@ -4416,19 +4416,19 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> /* Handle as an unconditional branch to get correct delay
> slot checking. */
> blink = 31;
> - btgt = ctx->pc + insn_bytes + delayslot_size;
> + btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
> ctx->hflags |= MIPS_HFLAG_B;
> break;
> case OPC_BLTZALL: /* 0 < 0 likely */
> - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
> + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
> /* Skip the instruction in the delay slot */
> - ctx->pc += 4;
> + ctx->base.pc_next += 4;
> goto out;
> case OPC_BNEL: /* rx != rx likely */
> case OPC_BGTZL: /* 0 > 0 likely */
> case OPC_BLTZL: /* 0 < 0 likely */
> /* Skip the instruction in the delay slot */
> - ctx->pc += 4;
> + ctx->base.pc_next += 4;
> goto out;
> case OPC_J:
> ctx->hflags |= MIPS_HFLAG_B;
> @@ -4540,7 +4540,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> int post_delay = insn_bytes + delayslot_size;
> int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
>
> - tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit);
> + tcg_gen_movi_tl(cpu_gpr[blink],
> + ctx->base.pc_next + post_delay + lowbit);
> }
>
> out:
> @@ -5322,18 +5323,18 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> /* Mark as an IO operation because we read the time. */
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> gen_helper_mfc0_count(arg, cpu_env);
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_end();
> }
> /* Break the TB to be able to take timer interrupts immediately
> after reading count. DISAS_STOP isn't sufficient, we need to
> ensure we break completely out of translated code. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Count";
> break;
> /* 6,7 are implementation dependent */
> @@ -5729,7 +5730,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> if (sel != 0)
> check_insn(ctx, ISA_MIPS32);
>
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
>
> @@ -5901,7 +5902,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_pagegrain(cpu_env, arg);
> rn = "PageGrain";
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 2:
> CP0_CHECK(ctx->sc);
> @@ -5962,7 +5963,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_hwrena(cpu_env, arg);
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "HWREna";
> break;
> default:
> @@ -6025,29 +6026,29 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> save_cpu_state(ctx, 1);
> gen_helper_mtc0_status(cpu_env, arg);
> /* DISAS_STOP isn't good enough here, hflags may have changed. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Status";
> break;
> case 1:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_intctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "IntCtl";
> break;
> case 2:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_srsctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "SRSCtl";
> break;
> case 3:
> check_insn(ctx, ISA_MIPS32R2);
> gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "SRSMap";
> break;
> default:
> @@ -6062,8 +6063,8 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* Stop translation as we may have triggered an interrupt.
> * DISAS_STOP isn't sufficient, we need to ensure we break out of
> * translated code to check for pending interrupts. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Cause";
> break;
> default:
> @@ -6101,7 +6102,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config0(cpu_env, arg);
> rn = "Config";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 1:
> /* ignored, read only */
> @@ -6111,24 +6112,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config2(cpu_env, arg);
> rn = "Config2";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 3:
> gen_helper_mtc0_config3(cpu_env, arg);
> rn = "Config3";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 4:
> gen_helper_mtc0_config4(cpu_env, arg);
> rn = "Config4";
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 5:
> gen_helper_mtc0_config5(cpu_env, arg);
> rn = "Config5";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> /* 6,7 are implementation dependent */
> case 6:
> @@ -6218,34 +6219,34 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
> /* DISAS_STOP isn't good enough here, hflags may have changed. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Debug";
> break;
> case 1:
> // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
> rn = "TraceControl";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
> rn = "TraceControl2";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> goto cp0_unimplemented;
> case 3:
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
> rn = "UserTraceData";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "TraceBPC";
> goto cp0_unimplemented;
> default:
> @@ -6305,7 +6306,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> gen_helper_mtc0_errctl(cpu_env, arg);
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "ErrCtl";
> break;
> default:
> @@ -6396,12 +6397,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> trace_mips_translate_c0("mtc0", rn, reg, sel);
>
> /* For simplicity assume that all writes can cause interrupts. */
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_end();
> /* DISAS_STOP isn't sufficient, we need to ensure we break out of
> * translated code to check for pending interrupts. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> }
> return;
>
> @@ -6674,18 +6675,18 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> /* Mark as an IO operation because we read the time. */
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> gen_helper_mfc0_count(arg, cpu_env);
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_end();
> }
> /* Break the TB to be able to take timer interrupts immediately
> after reading count. DISAS_STOP isn't sufficient, we need to
> ensure we break completely out of translated code. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Count";
> break;
> /* 6,7 are implementation dependent */
> @@ -7067,7 +7068,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> if (sel != 0)
> check_insn(ctx, ISA_MIPS64);
>
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
>
> @@ -7297,7 +7298,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_hwrena(cpu_env, arg);
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "HWREna";
> break;
> default:
> @@ -7333,7 +7334,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> goto cp0_unimplemented;
> }
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 10:
> switch (sel) {
> @@ -7356,7 +7357,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> goto cp0_unimplemented;
> }
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 12:
> switch (sel) {
> @@ -7364,29 +7365,29 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> save_cpu_state(ctx, 1);
> gen_helper_mtc0_status(cpu_env, arg);
> /* DISAS_STOP isn't good enough here, hflags may have changed. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Status";
> break;
> case 1:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_intctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "IntCtl";
> break;
> case 2:
> check_insn(ctx, ISA_MIPS32R2);
> gen_helper_mtc0_srsctl(cpu_env, arg);
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "SRSCtl";
> break;
> case 3:
> check_insn(ctx, ISA_MIPS32R2);
> gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "SRSMap";
> break;
> default:
> @@ -7401,8 +7402,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* Stop translation as we may have triggered an intetrupt.
> * DISAS_STOP isn't sufficient, we need to ensure we break out of
> * translated code to check for pending interrupts. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Cause";
> break;
> default:
> @@ -7440,7 +7441,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config0(cpu_env, arg);
> rn = "Config";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 1:
> /* ignored, read only */
> @@ -7450,13 +7451,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config2(cpu_env, arg);
> rn = "Config2";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 3:
> gen_helper_mtc0_config3(cpu_env, arg);
> rn = "Config3";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case 4:
> /* currently ignored */
> @@ -7466,7 +7467,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_config5(cpu_env, arg);
> rn = "Config5";
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> /* 6,7 are implementation dependent */
> default:
> @@ -7546,32 +7547,32 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 0:
> gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
> /* DISAS_STOP isn't good enough here, hflags may have changed. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> rn = "Debug";
> break;
> case 1:
> // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "TraceControl";
> goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "TraceControl2";
> goto cp0_unimplemented;
> case 3:
> // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "UserTraceData";
> goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "TraceBPC";
> goto cp0_unimplemented;
> default:
> @@ -7631,7 +7632,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> switch (sel) {
> case 0:
> gen_helper_mtc0_errctl(cpu_env, arg);
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> rn = "ErrCtl";
> break;
> default:
> @@ -7722,12 +7723,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> trace_mips_translate_c0("dmtc0", rn, reg, sel);
>
> /* For simplicity assume that all writes can cause interrupts. */
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_end();
> /* DISAS_STOP isn't sufficient, we need to ensure we break out of
> * translated code to check for pending interrupts. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> }
> return;
>
> @@ -8138,7 +8139,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
> tcg_temp_free_i32(fs_tmp);
> }
> /* Stop translation as we may have changed hflags */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> /* COP2: Not implemented. */
> case 4:
> @@ -8297,7 +8298,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
> check_insn(ctx, ISA_MIPS2);
> gen_helper_eret(cpu_env);
> }
> - ctx->is_jmp = DISAS_EXCP;
> + ctx->base.is_jmp = DISAS_EXCP;
> }
> break;
> case OPC_DERET:
> @@ -8312,7 +8313,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
> generate_exception_end(ctx, EXCP_RI);
> } else {
> gen_helper_deret(cpu_env);
> - ctx->is_jmp = DISAS_EXCP;
> + ctx->base.is_jmp = DISAS_EXCP;
> }
> break;
> case OPC_WAIT:
> @@ -8323,11 +8324,11 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
> goto die;
> }
> /* If we get an exception, we want to restart at next instruction */
> - ctx->pc += 4;
> + ctx->base.pc_next += 4;
> save_cpu_state(ctx, 1);
> - ctx->pc -= 4;
> + ctx->base.pc_next -= 4;
> gen_helper_wait(cpu_env);
> - ctx->is_jmp = DISAS_EXCP;
> + ctx->base.is_jmp = DISAS_EXCP;
> break;
> default:
> die:
> @@ -8354,7 +8355,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
> if (cc != 0)
> check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
>
> - btarget = ctx->pc + 4 + offset;
> + btarget = ctx->base.pc_next + 4 + offset;
>
> switch (op) {
> case OPC_BC1F:
> @@ -8457,7 +8458,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
> if (ctx->hflags & MIPS_HFLAG_BMASK) {
> #ifdef MIPS_DEBUG_DISAS
> LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
> - "\n", ctx->pc);
> + "\n", ctx->base.pc_next);
> #endif
> generate_exception_end(ctx, EXCP_RI);
> goto out;
> @@ -8466,7 +8467,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
> gen_load_fpr64(ctx, t0, ft);
> tcg_gen_andi_i64(t0, t0, 1);
>
> - btarget = addr_add(ctx, ctx->pc + 4, offset);
> + btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
>
> switch (op) {
> case OPC_BC1EQZ:
> @@ -8752,7 +8753,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
> tcg_temp_free_i32(fs_tmp);
> }
> /* Stop translation as we may have changed hflags */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> #if defined(TARGET_MIPS64)
> case OPC_DMFC1:
> @@ -10751,19 +10752,19 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
> gen_store_gpr(t0, rt);
> break;
> case 2:
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> gen_helper_rdhwr_cc(t0, cpu_env);
> - if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_end();
> }
> gen_store_gpr(t0, rt);
> /* Break the TB to be able to take timer interrupts immediately
> after reading count. DISAS_STOP isn't sufficient, we need to ensure
> we break completely out of translated code. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> break;
> case 3:
> gen_helper_rdhwr_ccres(t0, cpu_env);
> @@ -10813,7 +10814,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
> static inline void clear_branch_hflags(DisasContext *ctx)
> {
> ctx->hflags &= ~MIPS_HFLAG_BMASK;
> - if (ctx->is_jmp == DISAS_NEXT) {
> + if (ctx->base.is_jmp == DISAS_NEXT) {
> save_cpu_state(ctx, 0);
> } else {
> /* it is not safe to save ctx->hflags as hflags may be changed
> @@ -10828,11 +10829,11 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
> int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
> /* Branches completion */
> clear_branch_hflags(ctx);
> - ctx->is_jmp = DISAS_NORETURN;
> + ctx->base.is_jmp = DISAS_NORETURN;
> /* FIXME: Need to clear can_do_io. */
> switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
> case MIPS_HFLAG_FBNSLOT:
> - gen_goto_tb(ctx, 0, ctx->pc + insn_bytes);
> + gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes);
> break;
> case MIPS_HFLAG_B:
> /* unconditional branch */
> @@ -10851,7 +10852,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
> TCGLabel *l1 = gen_new_label();
>
> tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
> - gen_goto_tb(ctx, 1, ctx->pc + insn_bytes);
> + gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes);
> gen_set_label(l1);
> gen_goto_tb(ctx, 0, ctx->btarget);
> }
> @@ -10874,7 +10875,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
> } else {
> tcg_gen_mov_tl(cpu_PC, btarget);
> }
> - if (ctx->singlestep_enabled) {
> + if (ctx->base.singlestep_enabled) {
> save_cpu_state(ctx, 0);
> gen_helper_raise_exception_debug(cpu_env);
> }
> @@ -10899,7 +10900,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
> if (ctx->hflags & MIPS_HFLAG_BMASK) {
> #ifdef MIPS_DEBUG_DISAS
> LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
> - "\n", ctx->pc);
> + "\n", ctx->base.pc_next);
> #endif
> generate_exception_end(ctx, EXCP_RI);
> goto out;
> @@ -10913,10 +10914,10 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
> gen_load_gpr(t0, rs);
> gen_load_gpr(t1, rt);
> bcond_compute = 1;
> - ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
> + ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
> if (rs <= rt && rs == 0) {
> /* OPC_BEQZALC, OPC_BNEZALC */
> - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
> + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
> }
> break;
> case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
> @@ -10924,23 +10925,23 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
> gen_load_gpr(t0, rs);
> gen_load_gpr(t1, rt);
> bcond_compute = 1;
> - ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
> + ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
> break;
> case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
> case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
> if (rs == 0 || rs == rt) {
> /* OPC_BLEZALC, OPC_BGEZALC */
> /* OPC_BGTZALC, OPC_BLTZALC */
> - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
> + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
> }
> gen_load_gpr(t0, rs);
> gen_load_gpr(t1, rt);
> bcond_compute = 1;
> - ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
> + ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
> break;
> case OPC_BC:
> case OPC_BALC:
> - ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
> + ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
> break;
> case OPC_BEQZC:
> case OPC_BNEZC:
> @@ -10948,7 +10949,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
> /* OPC_BEQZC, OPC_BNEZC */
> gen_load_gpr(t0, rs);
> bcond_compute = 1;
> - ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
> + ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
> } else {
> /* OPC_JIC, OPC_JIALC */
> TCGv tbase = tcg_temp_new();
> @@ -10971,13 +10972,13 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
> /* Uncoditional compact branch */
> switch (opc) {
> case OPC_JIALC:
> - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
> + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
> /* Fallthrough */
> case OPC_JIC:
> ctx->hflags |= MIPS_HFLAG_BR;
> break;
> case OPC_BALC:
> - tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
> + tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
> /* Fallthrough */
> case OPC_BC:
> ctx->hflags |= MIPS_HFLAG_B;
> @@ -11602,7 +11603,7 @@ static void decode_i64_mips16 (DisasContext *ctx,
>
> static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
> {
> - int extend = cpu_lduw_code(env, ctx->pc + 2);
> + int extend = cpu_lduw_code(env, ctx->base.pc_next + 2);
> int op, rx, ry, funct, sa;
> int16_t imm, offset;
>
> @@ -11842,7 +11843,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
> /* No delay slot, so just process as a normal instruction */
> break;
> case M16_OPC_JAL:
> - offset = cpu_lduw_code(env, ctx->pc + 2);
> + offset = cpu_lduw_code(env, ctx->base.pc_next + 2);
> offset = (((ctx->opcode & 0x1f) << 21)
> | ((ctx->opcode >> 5) & 0x1f) << 16
> | offset) << 2;
> @@ -13570,7 +13571,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
> gen_helper_di(t0, cpu_env);
> gen_store_gpr(t0, rs);
> /* Stop translation as we may have switched the execution mode */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> tcg_temp_free(t0);
> }
> break;
> @@ -13584,8 +13585,8 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
> gen_store_gpr(t0, rs);
> /* DISAS_STOP isn't sufficient, we need to ensure we break out
> of translated code to check for pending interrupts. */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> tcg_temp_free(t0);
> }
> break;
> @@ -13940,7 +13941,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
> uint32_t op, minor, minor2, mips32_op;
> uint32_t cond, fmt, cc;
>
> - insn = cpu_lduw_code(env, ctx->pc + 2);
> + insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
> ctx->opcode = (ctx->opcode << 16) | insn;
>
> rt = (ctx->opcode >> 21) & 0x1f;
> @@ -14741,7 +14742,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
> /* SYNCI */
> /* Break the TB to be able to sync copied instructions
> immediately */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> } else {
> /* TNEI */
> mips32_op = OPC_TNEI;
> @@ -14772,7 +14773,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> /* Break the TB to be able to sync copied instructions
> immediately */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case BC2F:
> case BC2T:
> @@ -15135,16 +15136,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
> /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
> switch ((ctx->opcode >> 16) & 0x1f) {
> case ADDIUPC_00 ... ADDIUPC_07:
> - gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
> + gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt);
> break;
> case AUIPC:
> - gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
> + gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt);
> break;
> case ALUIPC:
> - gen_pcrel(ctx, OPC_ALUIPC, ctx->pc, rt);
> + gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt);
> break;
> case LWPC_08 ... LWPC_0F:
> - gen_pcrel(ctx, R6_OPC_LWPC, ctx->pc & ~0x3, rt);
> + gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt);
> break;
> default:
> generate_exception(ctx, EXCP_RI);
> @@ -15276,8 +15277,8 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
> uint32_t op;
>
> /* make sure instructions are on a halfword boundary */
> - if (ctx->pc & 0x1) {
> - env->CP0_BadVAddr = ctx->pc;
> + if (ctx->base.pc_next & 0x1) {
> + env->CP0_BadVAddr = ctx->base.pc_next;
> generate_exception_end(ctx, EXCP_AdEL);
> return 2;
> }
> @@ -18503,7 +18504,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
> break;
> }
>
> - ctx->btarget = ctx->pc + (s16 << 2) + 4;
> + ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
>
> ctx->hflags |= MIPS_HFLAG_BC;
> ctx->hflags |= MIPS_HFLAG_BDS32;
> @@ -19524,8 +19525,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> int16_t imm;
>
> /* make sure instructions are on a word boundary */
> - if (ctx->pc & 0x3) {
> - env->CP0_BadVAddr = ctx->pc;
> + if (ctx->base.pc_next & 0x3) {
> + env->CP0_BadVAddr = ctx->base.pc_next;
> generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
> return;
> }
> @@ -19536,7 +19537,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>
> tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
> tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
> - gen_goto_tb(ctx, 1, ctx->pc + 4);
> + gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
> gen_set_label(l1);
> }
>
> @@ -19597,7 +19598,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> check_insn(ctx, ISA_MIPS32R2);
> /* Break the TB to be able to sync copied instructions
> immediately */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case OPC_BPOSGE32: /* MIPS DSP branch */
> #if defined(TARGET_MIPS64)
> @@ -19700,7 +19701,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> gen_store_gpr(t0, rt);
> /* Stop translation as we may have switched
> the execution mode. */
> - ctx->is_jmp = DISAS_STOP;
> + ctx->base.is_jmp = DISAS_STOP;
> break;
> case OPC_EI:
> check_insn(ctx, ISA_MIPS32R2);
> @@ -19709,8 +19710,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> gen_store_gpr(t0, rt);
> /* DISAS_STOP isn't sufficient, we need to ensure we break
> out of translated code to check for pending interrupts */
> - gen_save_pc(ctx->pc + 4);
> - ctx->is_jmp = DISAS_EXCP;
> + gen_save_pc(ctx->base.pc_next + 4);
> + ctx->base.is_jmp = DISAS_EXCP;
> break;
> default: /* Invalid */
> MIPS_INVAL("mfmc0");
> @@ -20184,7 +20185,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> break;
> case OPC_PCREL:
> check_insn(ctx, ISA_MIPS32R6);
> - gen_pcrel(ctx, ctx->opcode, ctx->pc, rs);
> + gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
> break;
> default: /* Invalid */
> MIPS_INVAL("major opcode");
> @@ -20197,22 +20198,22 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> {
> CPUMIPSState *env = cs->env_ptr;
> DisasContext ctx;
> - target_ulong pc_start;
> target_ulong next_page_start;
> - int num_insns;
> int max_insns;
> int insn_bytes;
> int is_slot;
>
> - pc_start = tb->pc;
> - next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> - ctx.pc = pc_start;
> + ctx.base.tb = tb;
> + ctx.base.pc_first = tb->pc;
> + ctx.base.pc_next = tb->pc;
> + ctx.base.is_jmp = DISAS_NEXT;
> + ctx.base.singlestep_enabled = cs->singlestep_enabled;
> + ctx.base.num_insns = 0;
> +
> + next_page_start = (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> ctx.saved_pc = -1;
> - ctx.singlestep_enabled = cs->singlestep_enabled;
> ctx.insn_flags = env->insn_flags;
> ctx.CP0_Config1 = env->CP0_Config1;
> - ctx.tb = tb;
> - ctx.is_jmp = DISAS_NEXT;
> ctx.btarget = 0;
> ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
> @@ -20226,7 +20227,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
> ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
> /* Restore delay slot state from the tb context. */
> - ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
> + ctx.hflags = (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bits? */
> ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
> (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
> @@ -20242,7 +20243,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> #endif
> ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
> MO_UNALN : MO_ALIGN;
> - num_insns = 0;
> max_insns = tb_cflags(tb) & CF_COUNT_MASK;
> if (max_insns == 0) {
> max_insns = CF_COUNT_MASK;
> @@ -20253,36 +20253,37 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
>
> LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
> gen_tb_start(tb);
> - while (ctx.is_jmp == DISAS_NEXT) {
> - tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
> - num_insns++;
> + while (ctx.base.is_jmp == DISAS_NEXT) {
> + tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK,
> + ctx.btarget);
> + ctx.base.num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
> save_cpu_state(&ctx, 1);
> - ctx.is_jmp = DISAS_NORETURN;
> + ctx.base.is_jmp = DISAS_NORETURN;
> gen_helper_raise_exception_debug(cpu_env);
> /* The address covered by the breakpoint must be included in
> [tb->pc, tb->pc + tb->size) in order to for it to be
> properly cleared -- thus we increment the PC here so that
> the logic setting tb->size below does the right thing. */
> - ctx.pc += 4;
> + ctx.base.pc_next += 4;
> goto done_generating;
> }
>
> - if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
> + if (ctx.base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
> gen_io_start();
> }
>
> is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
> if (!(ctx.hflags & MIPS_HFLAG_M16)) {
> - ctx.opcode = cpu_ldl_code(env, ctx.pc);
> + ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next);
> insn_bytes = 4;
> decode_opc(env, &ctx);
> } else if (ctx.insn_flags & ASE_MICROMIPS) {
> - ctx.opcode = cpu_lduw_code(env, ctx.pc);
> + ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
> insn_bytes = decode_micromips_opc(env, &ctx);
> } else if (ctx.insn_flags & ASE_MIPS16) {
> - ctx.opcode = cpu_lduw_code(env, ctx.pc);
> + ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
> insn_bytes = decode_mips16_opc(env, &ctx);
> } else {
> generate_exception_end(&ctx, EXCP_RI);
> @@ -20306,17 +20307,18 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> if (is_slot) {
> gen_branch(&ctx, insn_bytes);
> }
> - ctx.pc += insn_bytes;
> + ctx.base.pc_next += insn_bytes;
>
> /* Execute a branch and its delay slot as a single instruction.
> This is what GDB expects and is consistent with what the
> hardware does (e.g. if a delay slot instruction faults, the
> reported PC is the PC of the branch). */
> - if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
> + if (ctx.base.singlestep_enabled &&
> + (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
> break;
> }
>
> - if (ctx.pc >= next_page_start) {
> + if (ctx.base.pc_next >= next_page_start) {
> break;
> }
>
> @@ -20324,8 +20326,9 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> break;
> }
>
> - if (num_insns >= max_insns)
> + if (ctx.base.num_insns >= max_insns) {
> break;
> + }
>
> if (singlestep)
> break;
> @@ -20333,17 +20336,17 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> if (tb_cflags(tb) & CF_LAST_IO) {
> gen_io_end();
> }
> - if (cs->singlestep_enabled && ctx.is_jmp != DISAS_NORETURN) {
> - save_cpu_state(&ctx, ctx.is_jmp != DISAS_EXCP);
> + if (ctx.base.singlestep_enabled && ctx.base.is_jmp != DISAS_NORETURN) {
> + save_cpu_state(&ctx, ctx.base.is_jmp != DISAS_EXCP);
> gen_helper_raise_exception_debug(cpu_env);
> } else {
> - switch (ctx.is_jmp) {
> + switch (ctx.base.is_jmp) {
> case DISAS_STOP:
> - gen_goto_tb(&ctx, 0, ctx.pc);
> + gen_goto_tb(&ctx, 0, ctx.base.pc_next);
> break;
> case DISAS_NEXT:
> save_cpu_state(&ctx, 0);
> - gen_goto_tb(&ctx, 0, ctx.pc);
> + gen_goto_tb(&ctx, 0, ctx.base.pc_next);
> break;
> case DISAS_EXCP:
> tcg_gen_exit_tb(0);
> @@ -20354,18 +20357,19 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> }
> }
> done_generating:
> - gen_tb_end(tb, num_insns);
> + gen_tb_end(tb, ctx.base.num_insns);
>
> - tb->size = ctx.pc - pc_start;
> - tb->icount = num_insns;
> + tb->size = ctx.base.pc_next - ctx.base.pc_first;
> + tb->icount = ctx.base.num_insns;
>
> #ifdef DEBUG_DISAS
> LOG_DISAS("\n");
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
> - && qemu_log_in_addr_range(pc_start)) {
> + && qemu_log_in_addr_range(ctx.base.pc_first)) {
> qemu_log_lock();
> - qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, ctx.pc - pc_start);
> + qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first));
> + log_target_disas(cs, ctx.base.pc_first,
> + ctx.base.pc_next - ctx.base.pc_first);
> qemu_log("\n");
> qemu_log_unlock();
> }
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (6 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 07/14] target/mips: convert to DisasContextBase Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-07 23:18 ` Philippe Mathieu-Daudé
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 09/14] target/mips: convert to TranslatorOps Emilio G. Cota
` (9 subsequent siblings)
17 siblings, 1 reply; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno, Yongbok Kim
No changes to the logic here; this is just to make the diff
that follows easier to read.
While at it, remove the unnecessary 'struct' in
'struct TranslationBlock'.
Note that checkpatch complains with a false positive:
ERROR: space prohibited after that '&' (ctx:WxW)
#75: FILE: target/mips/translate.c:20220:
+ ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
^
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/mips/translate.c | 166 ++++++++++++++++++++++++------------------------
1 file changed, 84 insertions(+), 82 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index aefd729..08bd140 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20194,55 +20194,57 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
CPUMIPSState *env = cs->env_ptr;
- DisasContext ctx;
+ DisasContext ctx1;
+ DisasContext *ctx = &ctx1;
target_ulong next_page_start;
int max_insns;
int insn_bytes;
int is_slot;
- ctx.base.tb = tb;
- ctx.base.pc_first = tb->pc;
- ctx.base.pc_next = tb->pc;
- ctx.base.is_jmp = DISAS_NEXT;
- ctx.base.singlestep_enabled = cs->singlestep_enabled;
- ctx.base.num_insns = 0;
-
- next_page_start = (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- ctx.saved_pc = -1;
- ctx.insn_flags = env->insn_flags;
- ctx.CP0_Config1 = env->CP0_Config1;
- ctx.btarget = 0;
- ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
- ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
- ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
- ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
- ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
- ctx.PAMask = env->PAMask;
- ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
- ctx.eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
- ctx.sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
- ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
- ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
+ ctx->base.tb = tb;
+ ctx->base.pc_first = tb->pc;
+ ctx->base.pc_next = tb->pc;
+ ctx->base.is_jmp = DISAS_NEXT;
+ ctx->base.singlestep_enabled = cs->singlestep_enabled;
+ ctx->base.num_insns = 0;
+
+ next_page_start = (ctx->base.pc_first & TARGET_PAGE_MASK) +
+ TARGET_PAGE_SIZE;
+ ctx->saved_pc = -1;
+ ctx->insn_flags = env->insn_flags;
+ ctx->CP0_Config1 = env->CP0_Config1;
+ ctx->btarget = 0;
+ ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
+ ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
+ ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
+ ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
+ ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
+ ctx->PAMask = env->PAMask;
+ ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
+ ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
+ ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
+ ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
+ ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
/* Restore delay slot state from the tb context. */
- ctx.hflags = (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bits? */
- ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
- ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
+ ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */
+ ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
+ ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
- ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
- ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
- ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
- ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
- restore_cpu_state(env, &ctx);
+ ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
+ ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
+ ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
- ctx.mem_idx = MIPS_HFLAG_UM;
+ ctx->mem_idx = MIPS_HFLAG_UM;
#else
- ctx.mem_idx = hflags_mmu_index(ctx.hflags);
+ ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
- MO_UNALN : MO_ALIGN;
+ ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
+ MO_UNALN : MO_ALIGN;
max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
@@ -20251,74 +20253,74 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
+ LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflags);
gen_tb_start(tb);
- while (ctx.base.is_jmp == DISAS_NEXT) {
- tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK,
- ctx.btarget);
- ctx.base.num_insns++;
-
- if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
- save_cpu_state(&ctx, 1);
- ctx.base.is_jmp = DISAS_NORETURN;
+ while (ctx->base.is_jmp == DISAS_NEXT) {
+ tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
+ ctx->btarget);
+ ctx->base.num_insns++;
+
+ if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) {
+ save_cpu_state(ctx, 1);
+ ctx->base.is_jmp = DISAS_NORETURN;
gen_helper_raise_exception_debug(cpu_env);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
- ctx.base.pc_next += 4;
+ ctx->base.pc_next += 4;
goto done_generating;
}
- if (ctx.base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
+ if (ctx->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
- is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
- if (!(ctx.hflags & MIPS_HFLAG_M16)) {
- ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next);
+ is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
+ if (!(ctx->hflags & MIPS_HFLAG_M16)) {
+ ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
- decode_opc(env, &ctx);
- } else if (ctx.insn_flags & ASE_MICROMIPS) {
- ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
- insn_bytes = decode_micromips_opc(env, &ctx);
- } else if (ctx.insn_flags & ASE_MIPS16) {
- ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
- insn_bytes = decode_mips16_opc(env, &ctx);
+ decode_opc(env, ctx);
+ } else if (ctx->insn_flags & ASE_MICROMIPS) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_micromips_opc(env, ctx);
+ } else if (ctx->insn_flags & ASE_MIPS16) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_mips16_opc(env, ctx);
} else {
- generate_exception_end(&ctx, EXCP_RI);
+ generate_exception_end(ctx, EXCP_RI);
break;
}
- if (ctx.hflags & MIPS_HFLAG_BMASK) {
- if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
MIPS_HFLAG_FBNSLOT))) {
/* force to generate branch as there is neither delay nor
forbidden slot */
is_slot = 1;
}
- if ((ctx.hflags & MIPS_HFLAG_M16) &&
- (ctx.hflags & MIPS_HFLAG_FBNSLOT)) {
+ if ((ctx->hflags & MIPS_HFLAG_M16) &&
+ (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
/* Force to generate branch as microMIPS R6 doesn't restrict
branches in the forbidden slot. */
is_slot = 1;
}
}
if (is_slot) {
- gen_branch(&ctx, insn_bytes);
+ gen_branch(ctx, insn_bytes);
}
- ctx.base.pc_next += insn_bytes;
+ ctx->base.pc_next += insn_bytes;
/* Execute a branch and its delay slot as a single instruction.
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (ctx.base.singlestep_enabled &&
- (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
+ if (ctx->base.singlestep_enabled &&
+ (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
break;
}
- if (ctx.base.pc_next >= next_page_start) {
+ if (ctx->base.pc_next >= next_page_start) {
break;
}
@@ -20326,7 +20328,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
break;
}
- if (ctx.base.num_insns >= max_insns) {
+ if (ctx->base.num_insns >= max_insns) {
break;
}
@@ -20336,17 +20338,17 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (ctx.base.singlestep_enabled && ctx.base.is_jmp != DISAS_NORETURN) {
- save_cpu_state(&ctx, ctx.base.is_jmp != DISAS_EXCP);
+ if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
+ save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXCP);
gen_helper_raise_exception_debug(cpu_env);
} else {
- switch (ctx.base.is_jmp) {
+ switch (ctx->base.is_jmp) {
case DISAS_STOP:
- gen_goto_tb(&ctx, 0, ctx.base.pc_next);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NEXT:
- save_cpu_state(&ctx, 0);
- gen_goto_tb(&ctx, 0, ctx.base.pc_next);
+ save_cpu_state(ctx, 0);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_EXCP:
tcg_gen_exit_tb(0);
@@ -20357,19 +20359,19 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
}
}
done_generating:
- gen_tb_end(tb, ctx.base.num_insns);
+ gen_tb_end(tb, ctx->base.num_insns);
- tb->size = ctx.base.pc_next - ctx.base.pc_first;
- tb->icount = ctx.base.num_insns;
+ tb->size = ctx->base.pc_next - ctx->base.pc_first;
+ tb->icount = ctx->base.num_insns;
#ifdef DEBUG_DISAS
LOG_DISAS("\n");
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(ctx.base.pc_first)) {
+ && qemu_log_in_addr_range(ctx->base.pc_first)) {
qemu_log_lock();
- qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first));
- log_target_disas(cs, ctx.base.pc_first,
- ctx.base.pc_next - ctx.base.pc_first);
+ qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first));
+ log_target_disas(cs, ctx->base.pc_first,
+ ctx->base.pc_next - ctx->base.pc_first);
qemu_log("\n");
qemu_log_unlock();
}
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext Emilio G. Cota
@ 2018-03-07 23:18 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 31+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-07 23:18 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel; +Cc: Yongbok Kim, Richard Henderson, Aurelien Jarno
On 03/01/2018 07:53 PM, Emilio G. Cota wrote:
> No changes to the logic here; this is just to make the diff
> that follows easier to read.
>
> While at it, remove the unnecessary 'struct' in
> 'struct TranslationBlock'.
>
> Note that checkpatch complains with a false positive:
> ERROR: space prohibited after that '&' (ctx:WxW)
> #75: FILE: target/mips/translate.c:20220:
> + ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> ^
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 166 ++++++++++++++++++++++++------------------------
> 1 file changed, 84 insertions(+), 82 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index aefd729..08bd140 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -20194,55 +20194,57 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> }
> }
>
> -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
> {
> CPUMIPSState *env = cs->env_ptr;
> - DisasContext ctx;
> + DisasContext ctx1;
> + DisasContext *ctx = &ctx1;
> target_ulong next_page_start;
> int max_insns;
> int insn_bytes;
> int is_slot;
>
> - ctx.base.tb = tb;
> - ctx.base.pc_first = tb->pc;
> - ctx.base.pc_next = tb->pc;
> - ctx.base.is_jmp = DISAS_NEXT;
> - ctx.base.singlestep_enabled = cs->singlestep_enabled;
> - ctx.base.num_insns = 0;
> -
> - next_page_start = (ctx.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> - ctx.saved_pc = -1;
> - ctx.insn_flags = env->insn_flags;
> - ctx.CP0_Config1 = env->CP0_Config1;
> - ctx.btarget = 0;
> - ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> - ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
> - ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
> - ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
> - ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
> - ctx.PAMask = env->PAMask;
> - ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
> - ctx.eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
> - ctx.sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
> - ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
> - ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
> + ctx->base.tb = tb;
> + ctx->base.pc_first = tb->pc;
> + ctx->base.pc_next = tb->pc;
> + ctx->base.is_jmp = DISAS_NEXT;
> + ctx->base.singlestep_enabled = cs->singlestep_enabled;
> + ctx->base.num_insns = 0;
> +
> + next_page_start = (ctx->base.pc_first & TARGET_PAGE_MASK) +
> + TARGET_PAGE_SIZE;
> + ctx->saved_pc = -1;
> + ctx->insn_flags = env->insn_flags;
> + ctx->CP0_Config1 = env->CP0_Config1;
> + ctx->btarget = 0;
> + ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> + ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
> + ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
> + ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
> + ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
> + ctx->PAMask = env->PAMask;
> + ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
> + ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
> + ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
> + ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
> + ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
> /* Restore delay slot state from the tb context. */
> - ctx.hflags = (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bits? */
> - ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> - ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
> + ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */
> + ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> + ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
> (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
> - ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
> - ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
> - ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
> - ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> - restore_cpu_state(env, &ctx);
> + ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
> + ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
> + ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
> + ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> + restore_cpu_state(env, ctx);
> #ifdef CONFIG_USER_ONLY
> - ctx.mem_idx = MIPS_HFLAG_UM;
> + ctx->mem_idx = MIPS_HFLAG_UM;
> #else
> - ctx.mem_idx = hflags_mmu_index(ctx.hflags);
> + ctx->mem_idx = hflags_mmu_index(ctx->hflags);
> #endif
> - ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
> - MO_UNALN : MO_ALIGN;
> + ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
> + MO_UNALN : MO_ALIGN;
> max_insns = tb_cflags(tb) & CF_COUNT_MASK;
> if (max_insns == 0) {
> max_insns = CF_COUNT_MASK;
> @@ -20251,74 +20253,74 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> max_insns = TCG_MAX_INSNS;
> }
>
> - LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
> + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflags);
> gen_tb_start(tb);
> - while (ctx.base.is_jmp == DISAS_NEXT) {
> - tcg_gen_insn_start(ctx.base.pc_next, ctx.hflags & MIPS_HFLAG_BMASK,
> - ctx.btarget);
> - ctx.base.num_insns++;
> -
> - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {
> - save_cpu_state(&ctx, 1);
> - ctx.base.is_jmp = DISAS_NORETURN;
> + while (ctx->base.is_jmp == DISAS_NEXT) {
> + tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
> + ctx->btarget);
> + ctx->base.num_insns++;
> +
> + if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) {
> + save_cpu_state(ctx, 1);
> + ctx->base.is_jmp = DISAS_NORETURN;
> gen_helper_raise_exception_debug(cpu_env);
> /* The address covered by the breakpoint must be included in
> [tb->pc, tb->pc + tb->size) in order to for it to be
> properly cleared -- thus we increment the PC here so that
> the logic setting tb->size below does the right thing. */
> - ctx.base.pc_next += 4;
> + ctx->base.pc_next += 4;
> goto done_generating;
> }
>
> - if (ctx.base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
> + if (ctx->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
> gen_io_start();
> }
>
> - is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
> - if (!(ctx.hflags & MIPS_HFLAG_M16)) {
> - ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next);
> + is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
> + if (!(ctx->hflags & MIPS_HFLAG_M16)) {
> + ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
> insn_bytes = 4;
> - decode_opc(env, &ctx);
> - } else if (ctx.insn_flags & ASE_MICROMIPS) {
> - ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
> - insn_bytes = decode_micromips_opc(env, &ctx);
> - } else if (ctx.insn_flags & ASE_MIPS16) {
> - ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);
> - insn_bytes = decode_mips16_opc(env, &ctx);
> + decode_opc(env, ctx);
> + } else if (ctx->insn_flags & ASE_MICROMIPS) {
> + ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
> + insn_bytes = decode_micromips_opc(env, ctx);
> + } else if (ctx->insn_flags & ASE_MIPS16) {
> + ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
> + insn_bytes = decode_mips16_opc(env, ctx);
> } else {
> - generate_exception_end(&ctx, EXCP_RI);
> + generate_exception_end(ctx, EXCP_RI);
> break;
> }
>
> - if (ctx.hflags & MIPS_HFLAG_BMASK) {
> - if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
> + if (ctx->hflags & MIPS_HFLAG_BMASK) {
> + if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
> MIPS_HFLAG_FBNSLOT))) {
> /* force to generate branch as there is neither delay nor
> forbidden slot */
> is_slot = 1;
> }
> - if ((ctx.hflags & MIPS_HFLAG_M16) &&
> - (ctx.hflags & MIPS_HFLAG_FBNSLOT)) {
> + if ((ctx->hflags & MIPS_HFLAG_M16) &&
> + (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
> /* Force to generate branch as microMIPS R6 doesn't restrict
> branches in the forbidden slot. */
> is_slot = 1;
> }
> }
> if (is_slot) {
> - gen_branch(&ctx, insn_bytes);
> + gen_branch(ctx, insn_bytes);
> }
> - ctx.base.pc_next += insn_bytes;
> + ctx->base.pc_next += insn_bytes;
>
> /* Execute a branch and its delay slot as a single instruction.
> This is what GDB expects and is consistent with what the
> hardware does (e.g. if a delay slot instruction faults, the
> reported PC is the PC of the branch). */
> - if (ctx.base.singlestep_enabled &&
> - (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
> + if (ctx->base.singlestep_enabled &&
> + (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
> break;
> }
>
> - if (ctx.base.pc_next >= next_page_start) {
> + if (ctx->base.pc_next >= next_page_start) {
> break;
> }
>
> @@ -20326,7 +20328,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> break;
> }
>
> - if (ctx.base.num_insns >= max_insns) {
> + if (ctx->base.num_insns >= max_insns) {
> break;
> }
>
> @@ -20336,17 +20338,17 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> if (tb_cflags(tb) & CF_LAST_IO) {
> gen_io_end();
> }
> - if (ctx.base.singlestep_enabled && ctx.base.is_jmp != DISAS_NORETURN) {
> - save_cpu_state(&ctx, ctx.base.is_jmp != DISAS_EXCP);
> + if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
> + save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXCP);
> gen_helper_raise_exception_debug(cpu_env);
> } else {
> - switch (ctx.base.is_jmp) {
> + switch (ctx->base.is_jmp) {
> case DISAS_STOP:
> - gen_goto_tb(&ctx, 0, ctx.base.pc_next);
> + gen_goto_tb(ctx, 0, ctx->base.pc_next);
> break;
> case DISAS_NEXT:
> - save_cpu_state(&ctx, 0);
> - gen_goto_tb(&ctx, 0, ctx.base.pc_next);
> + save_cpu_state(ctx, 0);
> + gen_goto_tb(ctx, 0, ctx->base.pc_next);
> break;
> case DISAS_EXCP:
> tcg_gen_exit_tb(0);
> @@ -20357,19 +20359,19 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> }
> }
> done_generating:
> - gen_tb_end(tb, ctx.base.num_insns);
> + gen_tb_end(tb, ctx->base.num_insns);
>
> - tb->size = ctx.base.pc_next - ctx.base.pc_first;
> - tb->icount = ctx.base.num_insns;
> + tb->size = ctx->base.pc_next - ctx->base.pc_first;
> + tb->icount = ctx->base.num_insns;
>
> #ifdef DEBUG_DISAS
> LOG_DISAS("\n");
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
> - && qemu_log_in_addr_range(ctx.base.pc_first)) {
> + && qemu_log_in_addr_range(ctx->base.pc_first)) {
> qemu_log_lock();
> - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first));
> - log_target_disas(cs, ctx.base.pc_first,
> - ctx.base.pc_next - ctx.base.pc_first);
> + qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first));
> + log_target_disas(cs, ctx->base.pc_first,
> + ctx->base.pc_next - ctx->base.pc_first);
> qemu_log("\n");
> qemu_log_unlock();
> }
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Qemu-devel] [PATCHv1 09/14] target/mips: convert to TranslatorOps
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (7 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 10/14] target/s390x: convert to DisasJumpType Emilio G. Cota
` (8 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Aurelien Jarno, Yongbok Kim
Notes:
- DISAS_TOO_MANY replaces the former "break" in the translation loop.
However, care must be taken not to overwrite a previous condition
in is_jmp; that's why in translate_insn we first check is_jmp and
return if it's != DISAS_NEXT.
- Added an assert in translate_insn, before exiting due to an exception,
to make sure that is_jmp is set to DISAS_EXCP (the exception generation
function always sets it.)
- Added an assert for the default case in is_jmp's switch.
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/mips/translate.c | 227 ++++++++++++++++++++++++------------------------
1 file changed, 113 insertions(+), 114 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 08bd140..f01139c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1432,6 +1432,7 @@ static TCGv_i64 msa_wr_d[64];
typedef struct DisasContext {
DisasContextBase base;
target_ulong saved_pc;
+ target_ulong next_page_start;
uint32_t opcode;
int insn_flags;
int32_t CP0_Config1;
@@ -20194,24 +20195,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUMIPSState *env = cs->env_ptr;
- DisasContext ctx1;
- DisasContext *ctx = &ctx1;
- target_ulong next_page_start;
- int max_insns;
- int insn_bytes;
- int is_slot;
-
- ctx->base.tb = tb;
- ctx->base.pc_first = tb->pc;
- ctx->base.pc_next = tb->pc;
- ctx->base.is_jmp = DISAS_NEXT;
- ctx->base.singlestep_enabled = cs->singlestep_enabled;
- ctx->base.num_insns = 0;
- next_page_start = (ctx->base.pc_first & TARGET_PAGE_MASK) +
+ ctx->next_page_start = (ctx->base.pc_first & TARGET_PAGE_MASK) +
TARGET_PAGE_SIZE;
ctx->saved_pc = -1;
ctx->insn_flags = env->insn_flags;
@@ -20245,99 +20234,102 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
#endif
ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
MO_UNALN : MO_ALIGN;
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
- LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflags);
- gen_tb_start(tb);
- while (ctx->base.is_jmp == DISAS_NEXT) {
- tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
- ctx->btarget);
- ctx->base.num_insns++;
+ LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
+ ctx->hflags);
+}
- if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) {
- save_cpu_state(ctx, 1);
- ctx->base.is_jmp = DISAS_NORETURN;
- gen_helper_raise_exception_debug(cpu_env);
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- ctx->base.pc_next += 4;
- goto done_generating;
- }
+static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
+{
+}
- if (ctx->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
- if (!(ctx->hflags & MIPS_HFLAG_M16)) {
- ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- insn_bytes = 4;
- decode_opc(env, ctx);
- } else if (ctx->insn_flags & ASE_MICROMIPS) {
- ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
- insn_bytes = decode_micromips_opc(env, ctx);
- } else if (ctx->insn_flags & ASE_MIPS16) {
- ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
- insn_bytes = decode_mips16_opc(env, ctx);
- } else {
- generate_exception_end(ctx, EXCP_RI);
- break;
- }
+ tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
+ ctx->btarget);
+}
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
- MIPS_HFLAG_FBNSLOT))) {
- /* force to generate branch as there is neither delay nor
- forbidden slot */
- is_slot = 1;
- }
- if ((ctx->hflags & MIPS_HFLAG_M16) &&
- (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
- /* Force to generate branch as microMIPS R6 doesn't restrict
- branches in the forbidden slot. */
- is_slot = 1;
- }
- }
- if (is_slot) {
- gen_branch(ctx, insn_bytes);
- }
- ctx->base.pc_next += insn_bytes;
+static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- /* Execute a branch and its delay slot as a single instruction.
- This is what GDB expects and is consistent with what the
- hardware does (e.g. if a delay slot instruction faults, the
- reported PC is the PC of the branch). */
- if (ctx->base.singlestep_enabled &&
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
- break;
- }
+ save_cpu_state(ctx, 1);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ gen_helper_raise_exception_debug(cpu_env);
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ ctx->base.pc_next += 4;
+ return true;
+}
- if (ctx->base.pc_next >= next_page_start) {
- break;
- }
+static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ CPUMIPSState *env = cs->env_ptr;
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ int insn_bytes;
+ int is_slot;
- if (tcg_op_buf_full()) {
- break;
- }
+ is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
+ if (!(ctx->hflags & MIPS_HFLAG_M16)) {
+ ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
+ insn_bytes = 4;
+ decode_opc(env, ctx);
+ } else if (ctx->insn_flags & ASE_MICROMIPS) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_micromips_opc(env, ctx);
+ } else if (ctx->insn_flags & ASE_MIPS16) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_mips16_opc(env, ctx);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ g_assert(ctx->base.is_jmp == DISAS_EXCP);
+ return;
+ }
- if (ctx->base.num_insns >= max_insns) {
- break;
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
+ MIPS_HFLAG_FBNSLOT))) {
+ /* force to generate branch as there is neither delay nor
+ forbidden slot */
+ is_slot = 1;
+ }
+ if ((ctx->hflags & MIPS_HFLAG_M16) &&
+ (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
+ /* Force to generate branch as microMIPS R6 doesn't restrict
+ branches in the forbidden slot. */
+ is_slot = 1;
}
+ }
+ if (is_slot) {
+ gen_branch(ctx, insn_bytes);
+ }
+ ctx->base.pc_next += insn_bytes;
- if (singlestep)
- break;
+ if (ctx->base.is_jmp != DISAS_NEXT) {
+ return;
}
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
+ /* Execute a branch and its delay slot as a single instruction.
+ This is what GDB expects and is consistent with what the
+ hardware does (e.g. if a delay slot instruction faults, the
+ reported PC is the PC of the branch). */
+ if (ctx->base.singlestep_enabled &&
+ (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+ if (ctx->base.pc_next >= ctx->next_page_start) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
}
+}
+
+static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXCP);
gen_helper_raise_exception_debug(cpu_env);
@@ -20347,6 +20339,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NEXT:
+ case DISAS_TOO_MANY:
save_cpu_state(ctx, 0);
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
@@ -20354,28 +20347,34 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_exit_tb(0);
break;
case DISAS_NORETURN:
- default:
break;
+ default:
+ g_assert_not_reached();
}
}
-done_generating:
- gen_tb_end(tb, ctx->base.num_insns);
-
- tb->size = ctx->base.pc_next - ctx->base.pc_first;
- tb->icount = ctx->base.num_insns;
-
-#ifdef DEBUG_DISAS
- LOG_DISAS("\n");
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(ctx->base.pc_first)) {
- qemu_log_lock();
- qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first));
- log_target_disas(cs, ctx->base.pc_first,
- ctx->base.pc_next - ctx->base.pc_first);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+}
+
+static void mips_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+ log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps mips_tr_ops = {
+ .init_disas_context = mips_tr_init_disas_context,
+ .tb_start = mips_tr_tb_start,
+ .insn_start = mips_tr_insn_start,
+ .breakpoint_check = mips_tr_breakpoint_check,
+ .translate_insn = mips_tr_translate_insn,
+ .tb_stop = mips_tr_tb_stop,
+ .disas_log = mips_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+{
+ DisasContext ctx;
+
+ translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
}
static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 10/14] target/s390x: convert to DisasJumpType
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (8 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 09/14] target/mips: convert to TranslatorOps Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-02 10:12 ` Cornelia Huck
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase Emilio G. Cota
` (7 subsequent siblings)
17 siblings, 1 reply; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, David Hildenbrand, Cornelia Huck,
Alexander Graf, qemu-s390x
The only non-trivial modification is the use of DISAS_TOO_MANY
in the same way is used by the generic translation loop.
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: qemu-s390x@nongnu.org
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/s390x/translate.c | 1267 +++++++++++++++++++++++-----------------------
1 file changed, 632 insertions(+), 635 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index b470d69..5346791 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -42,6 +42,7 @@
#include "exec/helper-gen.h"
#include "trace-tcg.h"
+#include "exec/translator.h"
#include "exec/log.h"
@@ -73,9 +74,6 @@ typedef struct {
} u;
} DisasCompare;
-/* is_jmp field values */
-#define DISAS_EXCP DISAS_TARGET_0
-
#ifdef DEBUG_INLINE_BRANCHES
static uint64_t inline_branch_hit[CC_OP_MAX];
static uint64_t inline_branch_miss[CC_OP_MAX];
@@ -1087,26 +1085,24 @@ typedef struct {
#define SPEC_r2_f128 16
/* Return values from translate_one, indicating the state of the TB. */
-typedef enum {
- /* Continue the TB. */
- NO_EXIT,
- /* We have emitted one or more goto_tb. No fixup required. */
- EXIT_GOTO_TB,
- /* We are not using a goto_tb (for whatever reason), but have updated
- the PC (for whatever reason), so there's no need to do it again on
- exiting the TB. */
- EXIT_PC_UPDATED,
- /* We have updated the PC and CC values. */
- EXIT_PC_CC_UPDATED,
- /* We are exiting the TB, but have neither emitted a goto_tb, nor
- updated the PC for the next instruction to be executed. */
- EXIT_PC_STALE,
- /* We are exiting the TB to the main loop. */
- EXIT_PC_STALE_NOCHAIN,
- /* We are ending the TB with a noreturn function call, e.g. longjmp.
- No following code will be executed. */
- EXIT_NORETURN,
-} ExitStatus;
+
+/* We are not using a goto_tb (for whatever reason), but have updated
+ the PC (for whatever reason), so there's no need to do it again on
+ exiting the TB. */
+#define DISAS_PC_UPDATED DISAS_TARGET_0
+
+/* We have emitted one or more goto_tb. No fixup required. */
+#define DISAS_GOTO_TB DISAS_TARGET_1
+
+/* We have updated the PC and CC values. */
+#define DISAS_PC_CC_UPDATED DISAS_TARGET_2
+
+/* We are exiting the TB, but have neither emitted a goto_tb, nor
+ updated the PC for the next instruction to be executed. */
+#define DISAS_PC_STALE DISAS_TARGET_3
+
+/* We are exiting the TB to the main loop. */
+#define DISAS_PC_STALE_NOCHAIN DISAS_TARGET_4
struct DisasInsn {
unsigned opc:16;
@@ -1121,7 +1117,7 @@ struct DisasInsn {
void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
void (*help_cout)(DisasContext *, DisasOps *);
- ExitStatus (*help_op)(DisasContext *, DisasOps *);
+ DisasJumpType (*help_op)(DisasContext *, DisasOps *);
uint64_t data;
};
@@ -1143,11 +1139,11 @@ static void help_l2_shift(DisasContext *s, DisasFields *f,
}
}
-static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
+static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
{
if (dest == s->next_pc) {
per_branch(s, true);
- return NO_EXIT;
+ return DISAS_NEXT;
}
if (use_goto_tb(s, dest)) {
update_cc_op(s);
@@ -1155,31 +1151,31 @@ static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
tcg_gen_goto_tb(0);
tcg_gen_movi_i64(psw_addr, dest);
tcg_gen_exit_tb((uintptr_t)s->tb);
- return EXIT_GOTO_TB;
+ return DISAS_GOTO_TB;
} else {
tcg_gen_movi_i64(psw_addr, dest);
per_branch(s, false);
- return EXIT_PC_UPDATED;
+ return DISAS_PC_UPDATED;
}
}
-static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
- bool is_imm, int imm, TCGv_i64 cdest)
+static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
+ bool is_imm, int imm, TCGv_i64 cdest)
{
- ExitStatus ret;
+ DisasJumpType ret;
uint64_t dest = s->pc + 2 * imm;
TCGLabel *lab;
/* Take care of the special cases first. */
if (c->cond == TCG_COND_NEVER) {
- ret = NO_EXIT;
+ ret = DISAS_NEXT;
goto egress;
}
if (is_imm) {
if (dest == s->next_pc) {
/* Branch to next. */
per_branch(s, true);
- ret = NO_EXIT;
+ ret = DISAS_NEXT;
goto egress;
}
if (c->cond == TCG_COND_ALWAYS) {
@@ -1189,13 +1185,13 @@ static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
} else {
if (!cdest) {
/* E.g. bcr %r0 -> no branch. */
- ret = NO_EXIT;
+ ret = DISAS_NEXT;
goto egress;
}
if (c->cond == TCG_COND_ALWAYS) {
tcg_gen_mov_i64(psw_addr, cdest);
per_branch(s, false);
- ret = EXIT_PC_UPDATED;
+ ret = DISAS_PC_UPDATED;
goto egress;
}
}
@@ -1224,7 +1220,7 @@ static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
tcg_gen_movi_i64(psw_addr, dest);
tcg_gen_exit_tb((uintptr_t)s->tb + 1);
- ret = EXIT_GOTO_TB;
+ ret = DISAS_GOTO_TB;
} else {
/* Fallthru can use goto_tb, but taken branch cannot. */
/* Store taken branch destination before the brcond. This
@@ -1252,7 +1248,7 @@ static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
tcg_gen_movi_i64(psw_addr, dest);
}
per_breaking_event(s);
- ret = EXIT_PC_UPDATED;
+ ret = DISAS_PC_UPDATED;
}
} else {
/* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
@@ -1286,7 +1282,7 @@ static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
}
tcg_temp_free_i64(next);
- ret = EXIT_PC_UPDATED;
+ ret = DISAS_PC_UPDATED;
}
egress:
@@ -1298,7 +1294,7 @@ static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
/* The operations. These perform the bulk of the work for any insn,
usually after the operands have been loaded and output initialized. */
-static ExitStatus op_abs(DisasContext *s, DisasOps *o)
+static DisasJumpType op_abs(DisasContext *s, DisasOps *o)
{
TCGv_i64 z, n;
z = tcg_const_i64(0);
@@ -1307,35 +1303,35 @@ static ExitStatus op_abs(DisasContext *s, DisasOps *o)
tcg_gen_movcond_i64(TCG_COND_LT, o->out, o->in2, z, n, o->in2);
tcg_temp_free_i64(n);
tcg_temp_free_i64(z);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_absf32(DisasContext *s, DisasOps *o)
{
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_absf64(DisasContext *s, DisasOps *o)
{
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
+static DisasJumpType op_absf128(DisasContext *s, DisasOps *o)
{
tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
tcg_gen_mov_i64(o->out2, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_add(DisasContext *s, DisasOps *o)
+static DisasJumpType op_add(DisasContext *s, DisasOps *o)
{
tcg_gen_add_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_addc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_addc(DisasContext *s, DisasOps *o)
{
DisasCompare cmp;
TCGv_i64 carry;
@@ -1359,10 +1355,10 @@ static ExitStatus op_addc(DisasContext *s, DisasOps *o)
tcg_gen_add_i64(o->out, o->out, carry);
tcg_temp_free_i64(carry);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_asi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_asi(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
@@ -1380,35 +1376,35 @@ static ExitStatus op_asi(DisasContext *s, DisasOps *o)
if (!s390_has_feat(S390_FEAT_STFLE_45)) {
tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_aeb(DisasContext *s, DisasOps *o)
{
gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_adb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_adb(DisasContext *s, DisasOps *o)
{
gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_axb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_axb(DisasContext *s, DisasOps *o)
{
gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_and(DisasContext *s, DisasOps *o)
+static DisasJumpType op_and(DisasContext *s, DisasOps *o)
{
tcg_gen_and_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_andi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_andi(DisasContext *s, DisasOps *o)
{
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
@@ -1422,10 +1418,10 @@ static ExitStatus op_andi(DisasContext *s, DisasOps *o)
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
set_cc_nz_u64(s, cc_dst);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ni(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
@@ -1443,28 +1439,28 @@ static ExitStatus op_ni(DisasContext *s, DisasOps *o)
if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_bas(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
{
tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
if (o->in2) {
tcg_gen_mov_i64(psw_addr, o->in2);
per_branch(s, false);
- return EXIT_PC_UPDATED;
+ return DISAS_PC_UPDATED;
} else {
- return NO_EXIT;
+ return DISAS_NEXT;
}
}
-static ExitStatus op_basi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
{
tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
}
-static ExitStatus op_bc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
{
int m1 = get_field(s->fields, m1);
bool is_imm = have_field(s->fields, i2);
@@ -1483,14 +1479,14 @@ static ExitStatus op_bc(DisasContext *s, DisasOps *o)
/* FIXME: perform checkpoint-synchronisation */
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
disas_jcc(s, &c, m1);
return help_branch(s, &c, is_imm, imm, o->in2);
}
-static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
bool is_imm = have_field(s->fields, i2);
@@ -1514,7 +1510,7 @@ static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
return help_branch(s, &c, is_imm, imm, o->in2);
}
-static ExitStatus op_bcth(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int imm = get_field(s->fields, i2);
@@ -1538,7 +1534,7 @@ static ExitStatus op_bcth(DisasContext *s, DisasOps *o)
return help_branch(s, &c, 1, imm, o->in2);
}
-static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
bool is_imm = have_field(s->fields, i2);
@@ -1557,7 +1553,7 @@ static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
return help_branch(s, &c, is_imm, imm, o->in2);
}
-static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -1583,7 +1579,7 @@ static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
return help_branch(s, &c, is_imm, imm, o->in2);
}
-static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_bx64(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -1609,7 +1605,7 @@ static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
return help_branch(s, &c, is_imm, imm, o->in2);
}
-static ExitStatus op_cj(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cj(DisasContext *s, DisasOps *o)
{
int imm, m3 = get_field(s->fields, m3);
bool is_imm;
@@ -1635,186 +1631,186 @@ static ExitStatus op_cj(DisasContext *s, DisasOps *o)
return help_branch(s, &c, is_imm, imm, o->out);
}
-static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ceb(DisasContext *s, DisasOps *o)
{
gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cdb(DisasContext *s, DisasOps *o)
{
gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cxb(DisasContext *s, DisasOps *o)
{
gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f32(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cfdb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f64(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f128(s, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cgeb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f32(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cgdb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f64(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f128(s, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clfeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clfeb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_clfeb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f32(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clfdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clfdb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_clfdb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f64(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clfxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f128(s, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clgeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clgeb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_clgeb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f32(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clgdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clgdb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_clgdb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f64(s, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clgxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m3);
tcg_temp_free_i32(m3);
gen_set_cc_nz_f128(s, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cegb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cegb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cdgb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_celgb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_celgb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_celgb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cdlgb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cdlgb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cdlgb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cxlgb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_cxlgb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cksm(DisasContext *s, DisasOps *o)
{
int r2 = get_field(s->fields, r2);
TCGv_i64 len = tcg_temp_new_i64();
@@ -1827,10 +1823,10 @@ static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
tcg_temp_free_i64(len);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
{
int l = get_field(s->fields, l1);
TCGv_i32 vl;
@@ -1857,13 +1853,13 @@ static ExitStatus op_clc(DisasContext *s, DisasOps *o)
gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
tcg_temp_free_i32(vl);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clcl(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r2 = get_field(s->fields, r2);
@@ -1872,7 +1868,7 @@ static ExitStatus op_clcl(DisasContext *s, DisasOps *o)
/* r1 and r2 must be even. */
if (r1 & 1 || r2 & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
t1 = tcg_const_i32(r1);
@@ -1881,10 +1877,10 @@ static ExitStatus op_clcl(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clcle(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -1893,7 +1889,7 @@ static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
/* r1 and r3 must be even. */
if (r1 & 1 || r3 & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
t1 = tcg_const_i32(r1);
@@ -1902,10 +1898,10 @@ static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clclu(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clclu(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -1914,7 +1910,7 @@ static ExitStatus op_clclu(DisasContext *s, DisasOps *o)
/* r1 and r3 must be even. */
if (r1 & 1 || r3 & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
t1 = tcg_const_i32(r1);
@@ -1923,10 +1919,10 @@ static ExitStatus op_clclu(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clm(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -1935,28 +1931,28 @@ static ExitStatus op_clm(DisasContext *s, DisasOps *o)
set_cc_static(s);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_clst(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clst(DisasContext *s, DisasOps *o)
{
gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
set_cc_static(s);
return_low128(o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cps(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cps(DisasContext *s, DisasOps *o)
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull);
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
tcg_gen_or_i64(o->out, o->out, t);
tcg_temp_free_i64(t);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cs(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
{
int d2 = get_field(s->fields, d2);
int b2 = get_field(s->fields, b2);
@@ -1978,10 +1974,10 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(cc);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -2004,10 +2000,10 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t_r3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_csst(DisasContext *s, DisasOps *o)
+static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s->fields, r3);
TCGv_i32 t_r3 = tcg_const_i32(r3);
@@ -2020,11 +2016,11 @@ static ExitStatus op_csst(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t_r3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_csp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
{
TCGMemOp mop = s->insn->data;
TCGv_i64 addr, old, cc;
@@ -2065,11 +2061,11 @@ static ExitStatus op_csp(DisasContext *s, DisasOps *o)
gen_helper_purge(cpu_env);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -2078,10 +2074,10 @@ static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t2);
tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
tcg_temp_free_i64(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ct(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ct(DisasContext *s, DisasOps *o)
{
int m3 = get_field(s->fields, m3);
TCGLabel *lab = gen_new_label();
@@ -2097,10 +2093,10 @@ static ExitStatus op_ct(DisasContext *s, DisasOps *o)
gen_trap(s);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_cuXX(DisasContext *s, DisasOps *o)
+static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o)
{
int m3 = get_field(s->fields, m3);
int r1 = get_field(s->fields, r1);
@@ -2110,7 +2106,7 @@ static ExitStatus op_cuXX(DisasContext *s, DisasOps *o)
/* R1 and R2 must both be even. */
if ((r1 | r2) & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
if (!s390_has_feat(S390_FEAT_ETF3_ENH)) {
m3 = 0;
@@ -2147,11 +2143,11 @@ static ExitStatus op_cuXX(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(tr2);
tcg_temp_free_i32(chk);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_diag(DisasContext *s, DisasOps *o)
+static DisasJumpType op_diag(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -2163,78 +2159,78 @@ static ExitStatus op_diag(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(func_code);
tcg_temp_free_i32(r3);
tcg_temp_free_i32(r1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_divs32(DisasContext *s, DisasOps *o)
{
gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
return_low128(o->out);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_divu32(DisasContext *s, DisasOps *o)
{
gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
return_low128(o->out);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_divs64(DisasContext *s, DisasOps *o)
{
gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
return_low128(o->out);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_divu64(DisasContext *s, DisasOps *o)
{
gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
return_low128(o->out);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_deb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_deb(DisasContext *s, DisasOps *o)
{
gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ddb(DisasContext *s, DisasOps *o)
{
gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_dxb(DisasContext *s, DisasOps *o)
{
gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ear(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ear(DisasContext *s, DisasOps *o)
{
int r2 = get_field(s->fields, r2);
tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ecag(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ecag(DisasContext *s, DisasOps *o)
{
/* No cache information provided. */
tcg_gen_movi_i64(o->out, -1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_efpc(DisasContext *s, DisasOps *o)
{
tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_epsw(DisasContext *s, DisasOps *o)
+static DisasJumpType op_epsw(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r2 = get_field(s->fields, r2);
@@ -2249,10 +2245,10 @@ static ExitStatus op_epsw(DisasContext *s, DisasOps *o)
}
tcg_temp_free_i64(t);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ex(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ex(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
TCGv_i32 ilen;
@@ -2261,7 +2257,7 @@ static ExitStatus op_ex(DisasContext *s, DisasOps *o)
/* Nested EXECUTE is not allowed. */
if (unlikely(s->ex_value)) {
gen_program_exception(s, PGM_EXECUTE);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
update_psw_addr(s);
@@ -2281,35 +2277,35 @@ static ExitStatus op_ex(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(v1);
}
- return EXIT_PC_CC_UPDATED;
+ return DISAS_PC_CC_UPDATED;
}
-static ExitStatus op_fieb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_fieb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_fieb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_fidb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_fidb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_fidb(o->out, cpu_env, o->in2, m3);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_fixb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_fixb(DisasContext *s, DisasOps *o)
{
TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m3);
return_low128(o->out2);
tcg_temp_free_i32(m3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
+static DisasJumpType op_flogr(DisasContext *s, DisasOps *o)
{
/* We'll use the original input for cc computation, since we get to
compare that against 0, which ought to be better than comparing
@@ -2326,10 +2322,10 @@ static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
tcg_gen_shr_i64(o->out2, o->out2, o->out);
tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_icm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
{
int m3 = get_field(s->fields, m3);
int pos, len, base = s->insn->data;
@@ -2386,18 +2382,18 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
tcg_gen_movi_i64(tmp, ccm);
gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
tcg_temp_free_i64(tmp);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_insi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_insi(DisasContext *s, DisasOps *o)
{
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ipm(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1;
@@ -2413,11 +2409,11 @@ static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
tcg_gen_shli_i64(t1, t1, 28);
tcg_gen_or_i64(o->out, o->out, t1);
tcg_temp_free_i64(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_idte(DisasContext *s, DisasOps *o)
+static DisasJumpType op_idte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
@@ -2429,10 +2425,10 @@ static ExitStatus op_idte(DisasContext *s, DisasOps *o)
}
gen_helper_idte(cpu_env, o->in1, o->in2, m4);
tcg_temp_free_i32(m4);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ipte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
@@ -2444,18 +2440,18 @@ static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
}
gen_helper_ipte(cpu_env, o->in1, o->in2, m4);
tcg_temp_free_i32(m4);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_iske(DisasContext *s, DisasOps *o)
+static DisasJumpType op_iske(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_iske(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_msa(DisasContext *s, DisasOps *o)
+static DisasJumpType op_msa(DisasContext *s, DisasOps *o)
{
int r1 = have_field(s->fields, r1) ? get_field(s->fields, r1) : 0;
int r2 = have_field(s->fields, r2) ? get_field(s->fields, r2) : 0;
@@ -2466,7 +2462,7 @@ static ExitStatus op_msa(DisasContext *s, DisasOps *o)
case S390_FEAT_TYPE_KMCTR:
if (r3 & 1 || !r3) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
/* FALL THROUGH */
case S390_FEAT_TYPE_PPNO:
@@ -2476,7 +2472,7 @@ static ExitStatus op_msa(DisasContext *s, DisasOps *o)
case S390_FEAT_TYPE_KM:
if (r1 & 1 || !r1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
/* FALL THROUGH */
case S390_FEAT_TYPE_KMAC:
@@ -2484,7 +2480,7 @@ static ExitStatus op_msa(DisasContext *s, DisasOps *o)
case S390_FEAT_TYPE_KLMD:
if (r2 & 1 || !r2) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
/* FALL THROUGH */
case S390_FEAT_TYPE_PCKMO:
@@ -2504,31 +2500,31 @@ static ExitStatus op_msa(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t_r2);
tcg_temp_free_i32(t_r3);
tcg_temp_free_i32(type);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_keb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_keb(DisasContext *s, DisasOps *o)
{
gen_helper_keb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_kdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_kdb(DisasContext *s, DisasOps *o)
{
gen_helper_kdb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_kxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_kxb(DisasContext *s, DisasOps *o)
{
gen_helper_kxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_laa(DisasContext *s, DisasOps *o)
+static DisasJumpType op_laa(DisasContext *s, DisasOps *o)
{
/* The real output is indeed the original value in memory;
recompute the addition for the computation of CC. */
@@ -2536,10 +2532,10 @@ static ExitStatus op_laa(DisasContext *s, DisasOps *o)
s->insn->data | MO_ALIGN);
/* However, we need to recompute the addition for setting CC. */
tcg_gen_add_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lan(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lan(DisasContext *s, DisasOps *o)
{
/* The real output is indeed the original value in memory;
recompute the addition for the computation of CC. */
@@ -2547,10 +2543,10 @@ static ExitStatus op_lan(DisasContext *s, DisasOps *o)
s->insn->data | MO_ALIGN);
/* However, we need to recompute the operation for setting CC. */
tcg_gen_and_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lao(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lao(DisasContext *s, DisasOps *o)
{
/* The real output is indeed the original value in memory;
recompute the addition for the computation of CC. */
@@ -2558,10 +2554,10 @@ static ExitStatus op_lao(DisasContext *s, DisasOps *o)
s->insn->data | MO_ALIGN);
/* However, we need to recompute the operation for setting CC. */
tcg_gen_or_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lax(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lax(DisasContext *s, DisasOps *o)
{
/* The real output is indeed the original value in memory;
recompute the addition for the computation of CC. */
@@ -2569,96 +2565,96 @@ static ExitStatus op_lax(DisasContext *s, DisasOps *o)
s->insn->data | MO_ALIGN);
/* However, we need to recompute the operation for setting CC. */
tcg_gen_xor_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ldeb(DisasContext *s, DisasOps *o)
{
gen_helper_ldeb(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ledb(DisasContext *s, DisasOps *o)
{
gen_helper_ledb(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o)
{
gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lexb(DisasContext *s, DisasOps *o)
{
gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o)
{
gen_helper_lxdb(o->out, cpu_env, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o)
{
gen_helper_lxeb(o->out, cpu_env, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
+static DisasJumpType op_llgt(DisasContext *s, DisasOps *o)
{
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld8s(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ld64(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lat(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
store_reg32_i64(get_field(s->fields, r1), o->in2);
@@ -2666,10 +2662,10 @@ static ExitStatus op_lat(DisasContext *s, DisasOps *o)
tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab);
gen_trap(s);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lgat(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lgat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
@@ -2677,10 +2673,10 @@ static ExitStatus op_lgat(DisasContext *s, DisasOps *o)
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lfhat(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lfhat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
store_reg32h_i64(get_field(s->fields, r1), o->in2);
@@ -2688,10 +2684,10 @@ static ExitStatus op_lfhat(DisasContext *s, DisasOps *o)
tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab);
gen_trap(s);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_llgfat(DisasContext *s, DisasOps *o)
+static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
@@ -2699,10 +2695,10 @@ static ExitStatus op_llgfat(DisasContext *s, DisasOps *o)
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_llgtat(DisasContext *s, DisasOps *o)
+static DisasJumpType op_llgtat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
@@ -2710,10 +2706,10 @@ static ExitStatus op_llgtat(DisasContext *s, DisasOps *o)
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_loc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
{
DisasCompare c;
@@ -2740,11 +2736,11 @@ static ExitStatus op_loc(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(z);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lctl(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -2753,10 +2749,10 @@ static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
- return EXIT_PC_STALE_NOCHAIN;
+ return DISAS_PC_STALE_NOCHAIN;
}
-static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -2765,26 +2761,26 @@ static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
- return EXIT_PC_STALE_NOCHAIN;
+ return DISAS_PC_STALE_NOCHAIN;
}
-static ExitStatus op_lra(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lra(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_lra(o->out, cpu_env, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lpp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lpp(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_st_i64(o->in2, cpu_env, offsetof(CPUS390XState, pp));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1, t2;
@@ -2801,10 +2797,10 @@ static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
gen_helper_load_psw(cpu_env, t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
-static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1, t2;
@@ -2819,21 +2815,21 @@ static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
gen_helper_load_psw(cpu_env, t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
#endif
-static ExitStatus op_lam(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lam(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
gen_helper_lam(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -2845,7 +2841,7 @@ static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32_i64(r1, t1);
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* First load the values of the first and last registers to trigger
@@ -2861,7 +2857,7 @@ static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
if (((r1 + 1) & 15) == r3) {
tcg_temp_free(t2);
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* Then load the remaining registers. Page fault can't occur. */
@@ -2876,10 +2872,10 @@ static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
tcg_temp_free(t2);
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -2891,7 +2887,7 @@ static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
store_reg32h_i64(r1, t1);
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* First load the values of the first and last registers to trigger
@@ -2907,7 +2903,7 @@ static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
if (((r1 + 1) & 15) == r3) {
tcg_temp_free(t2);
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* Then load the remaining registers. Page fault can't occur. */
@@ -2922,10 +2918,10 @@ static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
tcg_temp_free(t2);
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -2934,7 +2930,7 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
/* Only one register to read. */
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* First load the values of the first and last registers to trigger
@@ -2950,7 +2946,7 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
/* Only two registers to read. */
if (((r1 + 1) & 15) == r3) {
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* Then load the remaining registers. Page fault can't occur. */
@@ -2963,10 +2959,10 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
}
tcg_temp_free(t1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lpd(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
{
TCGv_i64 a1, a2;
TCGMemOp mop = s->insn->data;
@@ -2976,7 +2972,7 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o)
update_psw_addr(s);
update_cc_op(s);
gen_exception(EXCP_ATOMIC);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
/* In a serial context, perform the two loads ... */
@@ -2989,10 +2985,10 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o)
/* ... and indicate that we performed them while interlocked. */
gen_op_movi_cc(s, 0);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lpq(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
{
if (tb_cflags(s->tb) & CF_PARALLEL) {
gen_helper_lpq_parallel(o->out, cpu_env, o->in2);
@@ -3000,41 +2996,41 @@ static ExitStatus op_lpq(DisasContext *s, DisasOps *o)
gen_helper_lpq(o->out, cpu_env, o->in2);
}
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_lura(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lura(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_lura(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_lurag(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lurag(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_lurag(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_lzrb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_lzrb(DisasContext *s, DisasOps *o)
{
tcg_gen_andi_i64(o->out, o->in2, -256);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mov2(DisasContext *s, DisasOps *o)
{
o->out = o->in2;
o->g_out = o->g_in2;
o->in2 = NULL;
o->g_in2 = false;
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
{
int b2 = get_field(s->fields, b2);
TCGv ar1 = tcg_temp_new_i64();
@@ -3066,10 +3062,10 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1]));
tcg_temp_free_i64(ar1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_movx(DisasContext *s, DisasOps *o)
+static DisasJumpType op_movx(DisasContext *s, DisasOps *o)
{
o->out = o->in1;
o->out2 = o->in2;
@@ -3078,26 +3074,26 @@ static ExitStatus op_movx(DisasContext *s, DisasOps *o)
o->in1 = NULL;
o->in2 = NULL;
o->g_in1 = o->g_in2 = false;
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvc(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvcin(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_mvcin(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r2 = get_field(s->fields, r2);
@@ -3106,7 +3102,7 @@ static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
/* r1 and r2 must be even. */
if (r1 & 1 || r2 & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
t1 = tcg_const_i32(r1);
@@ -3115,10 +3111,10 @@ static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -3127,7 +3123,7 @@ static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
/* r1 and r3 must be even. */
if (r1 & 1 || r3 & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
t1 = tcg_const_i32(r1);
@@ -3136,10 +3132,10 @@ static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -3148,7 +3144,7 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
/* r1 and r3 must be even. */
if (r1 & 1 || r3 & 1) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
t1 = tcg_const_i32(r1);
@@ -3157,151 +3153,151 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvcos(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvcos(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s->fields, r3);
gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvcp(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, l1);
check_privileged(s);
gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, l1);
check_privileged(s);
gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_mvn(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvn(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_mvn(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvo(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvo(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_mvo(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o)
{
gen_helper_mvpg(cc_op, cpu_env, regs[0], o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvst(DisasContext *s, DisasOps *o)
{
gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
set_cc_static(s);
return_low128(o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mvz(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mvz(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_mvz(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mul(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mul(DisasContext *s, DisasOps *o)
{
tcg_gen_mul_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mul128(DisasContext *s, DisasOps *o)
{
tcg_gen_mulu2_i64(o->out2, o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_meeb(DisasContext *s, DisasOps *o)
{
gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mdeb(DisasContext *s, DisasOps *o)
{
gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mdb(DisasContext *s, DisasOps *o)
{
gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mxb(DisasContext *s, DisasOps *o)
{
gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o)
{
gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_maeb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_madb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_madb(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s->fields, r3);
gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mseb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s->fields, r3);
gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
+static DisasJumpType op_nabs(DisasContext *s, DisasOps *o)
{
TCGv_i64 z, n;
z = tcg_const_i64(0);
@@ -3310,78 +3306,78 @@ static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2);
tcg_temp_free_i64(n);
tcg_temp_free_i64(z);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_nabsf32(DisasContext *s, DisasOps *o)
{
tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_nabsf64(DisasContext *s, DisasOps *o)
{
tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
+static DisasJumpType op_nabsf128(DisasContext *s, DisasOps *o)
{
tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
tcg_gen_mov_i64(o->out2, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_nc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_nc(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_neg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_neg(DisasContext *s, DisasOps *o)
{
tcg_gen_neg_i64(o->out, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_negf32(DisasContext *s, DisasOps *o)
{
tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_negf64(DisasContext *s, DisasOps *o)
{
tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
+static DisasJumpType op_negf128(DisasContext *s, DisasOps *o)
{
tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
tcg_gen_mov_i64(o->out2, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_oc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_oc(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_or(DisasContext *s, DisasOps *o)
+static DisasJumpType op_or(DisasContext *s, DisasOps *o)
{
tcg_gen_or_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ori(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ori(DisasContext *s, DisasOps *o)
{
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
@@ -3394,10 +3390,10 @@ static ExitStatus op_ori(DisasContext *s, DisasOps *o)
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
set_cc_nz_u64(s, cc_dst);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_oi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_oi(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
@@ -3415,18 +3411,18 @@ static ExitStatus op_oi(DisasContext *s, DisasOps *o)
if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_pack(DisasContext *s, DisasOps *o)
+static DisasJumpType op_pack(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_pack(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_pka(DisasContext *s, DisasOps *o)
+static DisasJumpType op_pka(DisasContext *s, DisasOps *o)
{
int l2 = get_field(s->fields, l2) + 1;
TCGv_i32 l;
@@ -3434,15 +3430,15 @@ static ExitStatus op_pka(DisasContext *s, DisasOps *o)
/* The length must not exceed 32 bytes. */
if (l2 > 32) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
l = tcg_const_i32(l2);
gen_helper_pka(cpu_env, o->addr1, o->in2, l);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_pku(DisasContext *s, DisasOps *o)
+static DisasJumpType op_pku(DisasContext *s, DisasOps *o)
{
int l2 = get_field(s->fields, l2) + 1;
TCGv_i32 l;
@@ -3450,30 +3446,30 @@ static ExitStatus op_pku(DisasContext *s, DisasOps *o)
/* The length must be even and should not exceed 64 bytes. */
if ((l2 & 1) || (l2 > 64)) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
l = tcg_const_i32(l2);
gen_helper_pku(cpu_env, o->addr1, o->in2, l);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_popcnt(DisasContext *s, DisasOps *o)
+static DisasJumpType op_popcnt(DisasContext *s, DisasOps *o)
{
gen_helper_popcnt(o->out, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ptlb(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_ptlb(cpu_env);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_risbg(DisasContext *s, DisasOps *o)
{
int i3 = get_field(s->fields, i3);
int i4 = get_field(s->fields, i4);
@@ -3531,7 +3527,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
/* In some cases we can implement this with extract. */
if (imask == 0 && pos == 0 && len > 0 && len <= rot) {
tcg_gen_extract_i64(o->out, o->in2, 64 - rot, len);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* In some cases we can implement this with deposit. */
@@ -3560,10 +3556,10 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
tcg_gen_andi_i64(o->out, o->out, imask);
tcg_gen_or_i64(o->out, o->out, o->in2);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
{
int i3 = get_field(s->fields, i3);
int i4 = get_field(s->fields, i4);
@@ -3613,28 +3609,28 @@ static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
/* Set the CC. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
set_cc_nz_u64(s, cc_dst);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rev16(DisasContext *s, DisasOps *o)
{
tcg_gen_bswap16_i64(o->out, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rev32(DisasContext *s, DisasOps *o)
{
tcg_gen_bswap32_i64(o->out, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rev64(DisasContext *s, DisasOps *o)
{
tcg_gen_bswap64_i64(o->out, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rll32(DisasContext *s, DisasOps *o)
{
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -3646,34 +3642,34 @@ static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
tcg_temp_free_i32(to);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rll64(DisasContext *s, DisasOps *o)
{
tcg_gen_rotl_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rrbe(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_rrbe(cc_op, cpu_env, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sacf(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sacf(cpu_env, o->in2);
/* Addressing mode has changed, so end the block. */
- return EXIT_PC_STALE;
+ return DISAS_PC_STALE;
}
#endif
-static ExitStatus op_sam(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
{
int sam = s->insn->data;
TCGv_i64 tsam;
@@ -3696,7 +3692,7 @@ static ExitStatus op_sam(DisasContext *s, DisasOps *o)
documents that Bad Things Happen two bytes before the end. */
if (s->pc & ~mask) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
s->next_pc &= mask;
@@ -3705,64 +3701,64 @@ static ExitStatus op_sam(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tsam);
/* Always exit the TB, since we (may have) changed execution mode. */
- return EXIT_PC_STALE;
+ return DISAS_PC_STALE;
}
-static ExitStatus op_sar(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sar(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_seb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_seb(DisasContext *s, DisasOps *o)
{
gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sdb(DisasContext *s, DisasOps *o)
{
gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sxb(DisasContext *s, DisasOps *o)
{
gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sqeb(DisasContext *s, DisasOps *o)
{
gen_helper_sqeb(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sqdb(DisasContext *s, DisasOps *o)
{
gen_helper_sqdb(o->out, cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o)
{
gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
return_low128(o->out2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_servc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_servc(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sigp(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -3771,11 +3767,11 @@ static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
set_cc_static(s);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_soc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
{
DisasCompare c;
TCGv_i64 a, h;
@@ -3817,10 +3813,10 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(a);
gen_set_label(lab);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sla(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sla(DisasContext *s, DisasOps *o)
{
uint64_t sign = 1ull << s->insn->data;
enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
@@ -3831,40 +3827,40 @@ static ExitStatus op_sla(DisasContext *s, DisasOps *o)
tcg_gen_andi_i64(o->out, o->out, ~sign);
tcg_gen_andi_i64(o->in1, o->in1, sign);
tcg_gen_or_i64(o->out, o->out, o->in1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sll(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sll(DisasContext *s, DisasOps *o)
{
tcg_gen_shl_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sra(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sra(DisasContext *s, DisasOps *o)
{
tcg_gen_sar_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_srl(DisasContext *s, DisasOps *o)
+static DisasJumpType op_srl(DisasContext *s, DisasOps *o)
{
tcg_gen_shr_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sfpc(DisasContext *s, DisasOps *o)
{
gen_helper_sfpc(cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sfas(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sfas(DisasContext *s, DisasOps *o)
{
gen_helper_sfas(cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_srnm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_srnm(DisasContext *s, DisasOps *o)
{
int b2 = get_field(s->fields, b2);
int d2 = get_field(s->fields, d2);
@@ -3901,10 +3897,10 @@ static ExitStatus op_srnm(DisasContext *s, DisasOps *o)
/* Then install the new FPC to set the rounding mode in fpu_status. */
gen_helper_sfpc(cpu_env, t2);
tcg_temp_free_i64(t2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_spm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_spm(DisasContext *s, DisasOps *o)
{
tcg_gen_extrl_i64_i32(cc_op, o->in1);
tcg_gen_extract_i32(cc_op, cc_op, 28, 2);
@@ -3912,10 +3908,10 @@ static ExitStatus op_spm(DisasContext *s, DisasOps *o)
tcg_gen_shri_i64(o->in1, o->in1, 24);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in1, PSW_SHIFT_MASK_PM, 4);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ectg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
{
int b1 = get_field(s->fields, b1);
int d1 = get_field(s->fields, d1);
@@ -3942,49 +3938,49 @@ static ExitStatus op_ectg(DisasContext *s, DisasOps *o)
tcg_gen_mov_i64(regs[1], o->in2);
tcg_temp_free_i64(tmp);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_spka(DisasContext *s, DisasOps *o)
+static DisasJumpType op_spka(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_shri_i64(o->in2, o->in2, 4);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sske(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sske(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sske(cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ssm(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
- return EXIT_PC_STALE_NOCHAIN;
+ return DISAS_PC_STALE_NOCHAIN;
}
-static ExitStatus op_stap(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stap(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, core_id));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stck(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stck(DisasContext *s, DisasOps *o)
{
gen_helper_stck(o->out, cpu_env);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
{
TCGv_i64 c1 = tcg_temp_new_i64();
TCGv_i64 c2 = tcg_temp_new_i64();
@@ -4008,31 +4004,31 @@ static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(todpr);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sckc(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sckc(cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sckpf(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sckpf(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sckpf(cpu_env, regs[0]);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stckc(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stckc(o->out, cpu_env);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stctg(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -4040,10 +4036,10 @@ static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
gen_helper_stctg(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stctl(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -4051,187 +4047,187 @@ static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
gen_helper_stctl(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stidp(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid));
tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_ALIGN);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_spt(DisasContext *s, DisasOps *o)
+static DisasJumpType op_spt(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_spt(cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stfl(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stfl(cpu_env);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stpt(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stpt(o->out, cpu_env);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stsi(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_spx(DisasContext *s, DisasOps *o)
+static DisasJumpType op_spx(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_spx(cpu_env, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_xsch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_xsch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_xsch(cpu_env, regs[1]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_csch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_csch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_csch(cpu_env, regs[1]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_hsch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_hsch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_hsch(cpu_env, regs[1]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_msch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_msch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_msch(cpu_env, regs[1], o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rchp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rchp(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_rchp(cpu_env, regs[1]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rsch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rsch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_rsch(cpu_env, regs[1]);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sal(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sal(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sal(cpu_env, regs[1]);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_schm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_schm(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_schm(cpu_env, regs[1], regs[2], o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_siga(DisasContext *s, DisasOps *o)
+static DisasJumpType op_siga(DisasContext *s, DisasOps *o)
{
check_privileged(s);
/* From KVM code: Not provided, set CC = 3 for subchannel not operational */
gen_op_movi_cc(s, 3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stcps(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stcps(DisasContext *s, DisasOps *o)
{
check_privileged(s);
/* The instruction is suppressed if not provided. */
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ssch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ssch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_ssch(cpu_env, regs[1], o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stsch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stsch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stsch(cpu_env, regs[1], o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stcrw(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stcrw(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stcrw(cpu_env, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tpi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tpi(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_tpi(cc_op, cpu_env, o->addr1);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tsch(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tsch(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_tsch(cpu_env, regs[1], o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_chsc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_chsc(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_chsc(cpu_env, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stpx(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
{
uint64_t i2 = get_field(s->fields, i2);
TCGv_i64 t;
@@ -4254,66 +4250,66 @@ static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
}
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
- return EXIT_PC_STALE_NOCHAIN;
+ return DISAS_PC_STALE_NOCHAIN;
}
-static ExitStatus op_stura(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_stura(cpu_env, o->in2, o->in1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sturg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sturg(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sturg(cpu_env, o->in2, o->in1);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_stfle(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stfle(DisasContext *s, DisasOps *o)
{
gen_helper_stfle(cc_op, cpu_env, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_st8(DisasContext *s, DisasOps *o)
+static DisasJumpType op_st8(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_st16(DisasContext *s, DisasOps *o)
+static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_st32(DisasContext *s, DisasOps *o)
+static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_st64(DisasContext *s, DisasOps *o)
+static DisasJumpType op_st64(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stam(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stam(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
gen_helper_stam(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
{
int m3 = get_field(s->fields, m3);
int pos, base = s->insn->data;
@@ -4359,10 +4355,10 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
break;
}
tcg_temp_free_i64(tmp);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stm(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -4383,10 +4379,10 @@ static ExitStatus op_stm(DisasContext *s, DisasOps *o)
}
tcg_temp_free_i64(tsize);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
int r3 = get_field(s->fields, r3);
@@ -4407,20 +4403,20 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(t);
tcg_temp_free_i64(t4);
tcg_temp_free_i64(t32);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stpq(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
{
if (tb_cflags(s->tb) & CF_PARALLEL) {
gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out);
} else {
gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_srst(DisasContext *s, DisasOps *o)
+static DisasJumpType op_srst(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4430,10 +4426,10 @@ static ExitStatus op_srst(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_srstu(DisasContext *s, DisasOps *o)
+static DisasJumpType op_srstu(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4443,16 +4439,16 @@ static ExitStatus op_srstu(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sub(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sub(DisasContext *s, DisasOps *o)
{
tcg_gen_sub_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_subb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_subb(DisasContext *s, DisasOps *o)
{
DisasCompare cmp;
TCGv_i64 borrow;
@@ -4475,10 +4471,10 @@ static ExitStatus op_subb(DisasContext *s, DisasOps *o)
tcg_gen_sub_i64(o->out, o->out, borrow);
tcg_temp_free_i64(borrow);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_svc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_svc(DisasContext *s, DisasOps *o)
{
TCGv_i32 t;
@@ -4494,104 +4490,104 @@ static ExitStatus op_svc(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(t);
gen_exception(EXCP_SVC);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
-static ExitStatus op_tam(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tam(DisasContext *s, DisasOps *o)
{
int cc = 0;
cc |= (s->tb->flags & FLAG_MASK_64) ? 2 : 0;
cc |= (s->tb->flags & FLAG_MASK_32) ? 1 : 0;
gen_op_movi_cc(s, cc);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tceb(DisasContext *s, DisasOps *o)
{
gen_helper_tceb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tcdb(DisasContext *s, DisasOps *o)
{
gen_helper_tcdb(cc_op, cpu_env, o->in1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o)
{
gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_testblock(DisasContext *s, DisasOps *o)
+static DisasJumpType op_testblock(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_testblock(cc_op, cpu_env, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tprot(DisasContext *s, DisasOps *o)
{
gen_helper_tprot(cc_op, cpu_env, o->addr1, o->in2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
-static ExitStatus op_tp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tp(DisasContext *s, DisasOps *o)
{
TCGv_i32 l1 = tcg_const_i32(get_field(s->fields, l1) + 1);
gen_helper_tp(cc_op, cpu_env, o->addr1, l1);
tcg_temp_free_i32(l1);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tr(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tr(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_tr(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_tre(DisasContext *s, DisasOps *o)
+static DisasJumpType op_tre(DisasContext *s, DisasOps *o)
{
gen_helper_tre(o->out, cpu_env, o->out, o->out2, o->in2);
return_low128(o->out2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_trt(DisasContext *s, DisasOps *o)
+static DisasJumpType op_trt(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_trtr(DisasContext *s, DisasOps *o)
+static DisasJumpType op_trtr(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
+static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4619,28 +4615,28 @@ static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(sizes);
tcg_temp_free_i32(tst);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_ts(DisasContext *s, DisasOps *o)
+static DisasJumpType op_ts(DisasContext *s, DisasOps *o)
{
TCGv_i32 t1 = tcg_const_i32(0xff);
tcg_gen_atomic_xchg_i32(t1, o->in2, t1, get_mem_index(s), MO_UB);
tcg_gen_extract_i32(cc_op, t1, 7, 1);
tcg_temp_free_i32(t1);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
+static DisasJumpType op_unpk(DisasContext *s, DisasOps *o)
{
TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_unpka(DisasContext *s, DisasOps *o)
+static DisasJumpType op_unpka(DisasContext *s, DisasOps *o)
{
int l1 = get_field(s->fields, l1) + 1;
TCGv_i32 l;
@@ -4648,16 +4644,16 @@ static ExitStatus op_unpka(DisasContext *s, DisasOps *o)
/* The length must not exceed 32 bytes. */
if (l1 > 32) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
l = tcg_const_i32(l1);
gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_unpku(DisasContext *s, DisasOps *o)
+static DisasJumpType op_unpku(DisasContext *s, DisasOps *o)
{
int l1 = get_field(s->fields, l1) + 1;
TCGv_i32 l;
@@ -4665,17 +4661,17 @@ static ExitStatus op_unpku(DisasContext *s, DisasOps *o)
/* The length must be even and should not exceed 64 bytes. */
if ((l1 & 1) || (l1 > 64)) {
gen_program_exception(s, PGM_SPECIFICATION);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
l = tcg_const_i32(l1);
gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_xc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
{
int d1 = get_field(s->fields, d1);
int d2 = get_field(s->fields, d2);
@@ -4716,7 +4712,7 @@ static ExitStatus op_xc(DisasContext *s, DisasOps *o)
tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
}
gen_op_movi_cc(s, 0);
- return NO_EXIT;
+ return DISAS_NEXT;
}
/* But in general we'll defer to a helper. */
@@ -4725,16 +4721,16 @@ static ExitStatus op_xc(DisasContext *s, DisasOps *o)
gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2);
tcg_temp_free_i32(t32);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_xor(DisasContext *s, DisasOps *o)
+static DisasJumpType op_xor(DisasContext *s, DisasOps *o)
{
tcg_gen_xor_i64(o->out, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_xori(DisasContext *s, DisasOps *o)
+static DisasJumpType op_xori(DisasContext *s, DisasOps *o)
{
int shift = s->insn->data & 0xff;
int size = s->insn->data >> 8;
@@ -4747,10 +4743,10 @@ static ExitStatus op_xori(DisasContext *s, DisasOps *o)
/* Produce the CC from only the bits manipulated. */
tcg_gen_andi_i64(cc_dst, o->out, mask);
set_cc_nz_u64(s, cc_dst);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_xi(DisasContext *s, DisasOps *o)
+static DisasJumpType op_xi(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
@@ -4768,25 +4764,25 @@ static ExitStatus op_xi(DisasContext *s, DisasOps *o)
if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
}
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_zero(DisasContext *s, DisasOps *o)
+static DisasJumpType op_zero(DisasContext *s, DisasOps *o)
{
o->out = tcg_const_i64(0);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
+static DisasJumpType op_zero2(DisasContext *s, DisasOps *o)
{
o->out = tcg_const_i64(0);
o->out2 = o->out;
o->g_out2 = true;
- return NO_EXIT;
+ return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
-static ExitStatus op_clp(DisasContext *s, DisasOps *o)
+static DisasJumpType op_clp(DisasContext *s, DisasOps *o)
{
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4794,10 +4790,10 @@ static ExitStatus op_clp(DisasContext *s, DisasOps *o)
gen_helper_clp(cpu_env, r2);
tcg_temp_free_i32(r2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_pcilg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4807,10 +4803,10 @@ static ExitStatus op_pcilg(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_pcistg(DisasContext *s, DisasOps *o)
+static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4820,10 +4816,10 @@ static ExitStatus op_pcistg(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_stpcifc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
@@ -4833,17 +4829,17 @@ static ExitStatus op_stpcifc(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(ar);
tcg_temp_free_i32(r1);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_sic(DisasContext *s, DisasOps *o)
+static DisasJumpType op_sic(DisasContext *s, DisasOps *o)
{
check_privileged(s);
gen_helper_sic(cpu_env, o->in1, o->in2);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_rpcit(DisasContext *s, DisasOps *o)
+static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
@@ -4853,10 +4849,10 @@ static ExitStatus op_rpcit(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_pcistb(DisasContext *s, DisasOps *o)
+static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
@@ -4868,10 +4864,10 @@ static ExitStatus op_pcistb(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
-static ExitStatus op_mpcifc(DisasContext *s, DisasOps *o)
+static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
@@ -4881,7 +4877,7 @@ static ExitStatus op_mpcifc(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(ar);
tcg_temp_free_i32(r1);
set_cc_static(s);
- return NO_EXIT;
+ return DISAS_NEXT;
}
#endif
@@ -5983,10 +5979,10 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
return info;
}
-static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
+static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
{
const DisasInsn *insn;
- ExitStatus ret = NO_EXIT;
+ DisasJumpType ret = DISAS_NEXT;
DisasFields f;
DisasOps o;
@@ -5998,7 +5994,7 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
f.op, f.op2);
gen_illegal_opcode(s);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
#ifndef CONFIG_USER_ONLY
@@ -6045,7 +6041,7 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
}
if (excp) {
gen_program_exception(s, excp);
- return EXIT_NORETURN;
+ return DISAS_NORETURN;
}
}
@@ -6099,7 +6095,7 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
#ifndef CONFIG_USER_ONLY
if (s->tb->flags & FLAG_MASK_PER) {
/* An exception might be triggered, save PSW if not already done. */
- if (ret == NO_EXIT || ret == EXIT_PC_STALE) {
+ if (ret == DISAS_NEXT || ret == DISAS_PC_STALE) {
tcg_gen_movi_i64(psw_addr, s->next_pc);
}
@@ -6120,7 +6116,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
target_ulong pc_start;
uint64_t next_page_start;
int num_insns, max_insns;
- ExitStatus status;
+ DisasJumpType status;
bool do_debug;
pc_start = tb->pc;
@@ -6154,7 +6150,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
num_insns++;
if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
- status = EXIT_PC_STALE;
+ status = DISAS_PC_STALE;
do_debug = true;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
@@ -6172,39 +6168,40 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
/* If we reach a page boundary, are single stepping,
or exhaust instruction count, stop generation. */
- if (status == NO_EXIT
+ if (status == DISAS_NEXT
&& (dc.pc >= next_page_start
|| tcg_op_buf_full()
|| num_insns >= max_insns
|| singlestep
|| cs->singlestep_enabled
|| dc.ex_value)) {
- status = EXIT_PC_STALE;
+ status = DISAS_TOO_MANY;
}
- } while (status == NO_EXIT);
+ } while (status == DISAS_NEXT);
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
switch (status) {
- case EXIT_GOTO_TB:
- case EXIT_NORETURN:
+ case DISAS_GOTO_TB:
+ case DISAS_NORETURN:
break;
- case EXIT_PC_STALE:
- case EXIT_PC_STALE_NOCHAIN:
+ case DISAS_TOO_MANY:
+ case DISAS_PC_STALE:
+ case DISAS_PC_STALE_NOCHAIN:
update_psw_addr(&dc);
/* FALLTHRU */
- case EXIT_PC_UPDATED:
+ case DISAS_PC_UPDATED:
/* Next TB starts off with CC_OP_DYNAMIC, so make sure the
cc op type is in env */
update_cc_op(&dc);
/* FALLTHRU */
- case EXIT_PC_CC_UPDATED:
+ case DISAS_PC_CC_UPDATED:
/* Exit the TB, either by raising a debug exception or by return. */
if (do_debug) {
gen_exception(EXCP_DEBUG);
- } else if (use_exit_tb(&dc) || status == EXIT_PC_STALE_NOCHAIN) {
+ } else if (use_exit_tb(&dc) || status == DISAS_PC_STALE_NOCHAIN) {
tcg_gen_exit_tb(0);
} else {
tcg_gen_lookup_and_goto_ptr();
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 10/14] target/s390x: convert to DisasJumpType
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 10/14] target/s390x: convert to DisasJumpType Emilio G. Cota
@ 2018-03-02 10:12 ` Cornelia Huck
0 siblings, 0 replies; 31+ messages in thread
From: Cornelia Huck @ 2018-03-02 10:12 UTC (permalink / raw)
To: Emilio G. Cota
Cc: qemu-devel, Richard Henderson, David Hildenbrand, Alexander Graf,
qemu-s390x
On Thu, 1 Mar 2018 17:53:54 -0500
"Emilio G. Cota" <cota@braap.org> wrote:
> The only non-trivial modification is the use of DISAS_TOO_MANY
> in the same way is used by the generic translation loop.
>
> Reviewed-by: David Hildenbrand <david@redhat.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Cornelia Huck <cohuck@redhat.com>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> target/s390x/translate.c | 1267 +++++++++++++++++++++++-----------------------
> 1 file changed, 632 insertions(+), 635 deletions(-)
Acked-by: Cornelia Huck <cohuck@redhat.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (9 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 10/14] target/s390x: convert to DisasJumpType Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-02 9:34 ` David Hildenbrand
2018-03-02 10:12 ` Cornelia Huck
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps Emilio G. Cota
` (6 subsequent siblings)
17 siblings, 2 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, David Hildenbrand, Cornelia Huck,
Alexander Graf, qemu-s390x
Notes:
- Did not convert {num,max}_insns and is_jmp, since the corresponding
code will go away in the next patch.
- Avoided a checkpatch error in use_exit_tb.
- As suggested by David, (1) Drop ctx.pc and use
ctx.base.pc_next instead, and (2) Rename ctx.next_pc to
ctx.pc_tmp and add a comment about it.
Suggested-by: David Hildenbrand <david@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: qemu-s390x@nongnu.org
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/s390x/translate.c | 146 ++++++++++++++++++++++++-----------------------
1 file changed, 75 insertions(+), 71 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 5346791..c83a57f 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -52,14 +52,18 @@ typedef struct DisasInsn DisasInsn;
typedef struct DisasFields DisasFields;
struct DisasContext {
- struct TranslationBlock *tb;
+ DisasContextBase base;
const DisasInsn *insn;
DisasFields *fields;
uint64_t ex_value;
- uint64_t pc, next_pc;
+ /*
+ * During translate_one(), pc_tmp is used to determine the instruction
+ * to be executed after base.pc_next - e.g. next sequential instruction
+ * or a branch target.
+ */
+ uint64_t pc_tmp;
uint32_t ilen;
enum cc_op cc_op;
- bool singlestep_enabled;
};
/* Information carried about a condition to be evaluated. */
@@ -81,8 +85,8 @@ static uint64_t inline_branch_miss[CC_OP_MAX];
static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
{
- if (!(s->tb->flags & FLAG_MASK_64)) {
- if (s->tb->flags & FLAG_MASK_32) {
+ if (!(s->base.tb->flags & FLAG_MASK_64)) {
+ if (s->base.tb->flags & FLAG_MASK_32) {
return pc | 0x80000000;
}
}
@@ -188,16 +192,16 @@ static void return_low128(TCGv_i64 dest)
static void update_psw_addr(DisasContext *s)
{
/* psw.addr */
- tcg_gen_movi_i64(psw_addr, s->pc);
+ tcg_gen_movi_i64(psw_addr, s->base.pc_next);
}
static void per_branch(DisasContext *s, bool to_next)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_i64(gbea, s->pc);
+ tcg_gen_movi_i64(gbea, s->base.pc_next);
- if (s->tb->flags & FLAG_MASK_PER) {
- TCGv_i64 next_pc = to_next ? tcg_const_i64(s->next_pc) : psw_addr;
+ if (s->base.tb->flags & FLAG_MASK_PER) {
+ TCGv_i64 next_pc = to_next ? tcg_const_i64(s->pc_tmp) : psw_addr;
gen_helper_per_branch(cpu_env, gbea, next_pc);
if (to_next) {
tcg_temp_free_i64(next_pc);
@@ -210,16 +214,16 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
TCGv_i64 arg1, TCGv_i64 arg2)
{
#ifndef CONFIG_USER_ONLY
- if (s->tb->flags & FLAG_MASK_PER) {
+ if (s->base.tb->flags & FLAG_MASK_PER) {
TCGLabel *lab = gen_new_label();
tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab);
- tcg_gen_movi_i64(gbea, s->pc);
+ tcg_gen_movi_i64(gbea, s->base.pc_next);
gen_helper_per_branch(cpu_env, gbea, psw_addr);
gen_set_label(lab);
} else {
- TCGv_i64 pc = tcg_const_i64(s->pc);
+ TCGv_i64 pc = tcg_const_i64(s->base.pc_next);
tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc);
tcg_temp_free_i64(pc);
}
@@ -228,7 +232,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
static void per_breaking_event(DisasContext *s)
{
- tcg_gen_movi_i64(gbea, s->pc);
+ tcg_gen_movi_i64(gbea, s->base.pc_next);
}
static void update_cc_op(DisasContext *s)
@@ -250,7 +254,7 @@ static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
static int get_mem_index(DisasContext *s)
{
- switch (s->tb->flags & FLAG_MASK_ASC) {
+ switch (s->base.tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
return 0;
case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
@@ -315,7 +319,7 @@ static inline void gen_trap(DisasContext *s)
#ifndef CONFIG_USER_ONLY
static void check_privileged(DisasContext *s)
{
- if (s->tb->flags & FLAG_MASK_PSTATE) {
+ if (s->base.tb->flags & FLAG_MASK_PSTATE) {
gen_program_exception(s, PGM_PRIVILEGED);
}
}
@@ -324,7 +328,7 @@ static void check_privileged(DisasContext *s)
static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
{
TCGv_i64 tmp = tcg_temp_new_i64();
- bool need_31 = !(s->tb->flags & FLAG_MASK_64);
+ bool need_31 = !(s->base.tb->flags & FLAG_MASK_64);
/* Note that d2 is limited to 20 bits, signed. If we crop negative
displacements early we create larger immedate addends. */
@@ -537,9 +541,9 @@ static void gen_op_calc_cc(DisasContext *s)
static bool use_exit_tb(DisasContext *s)
{
- return (s->singlestep_enabled ||
- (tb_cflags(s->tb) & CF_LAST_IO) ||
- (s->tb->flags & FLAG_MASK_PER));
+ return s->base.singlestep_enabled ||
+ (tb_cflags(s->base.tb) & CF_LAST_IO) ||
+ (s->base.tb->flags & FLAG_MASK_PER);
}
static bool use_goto_tb(DisasContext *s, uint64_t dest)
@@ -548,8 +552,8 @@ static bool use_goto_tb(DisasContext *s, uint64_t dest)
return false;
}
#ifndef CONFIG_USER_ONLY
- return (dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) ||
- (dest & TARGET_PAGE_MASK) == (s->pc & TARGET_PAGE_MASK);
+ return (dest & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) ||
+ (dest & TARGET_PAGE_MASK) == (s->base.pc_next & TARGET_PAGE_MASK);
#else
return true;
#endif
@@ -1141,7 +1145,7 @@ static void help_l2_shift(DisasContext *s, DisasFields *f,
static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
{
- if (dest == s->next_pc) {
+ if (dest == s->pc_tmp) {
per_branch(s, true);
return DISAS_NEXT;
}
@@ -1150,7 +1154,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
per_breaking_event(s);
tcg_gen_goto_tb(0);
tcg_gen_movi_i64(psw_addr, dest);
- tcg_gen_exit_tb((uintptr_t)s->tb);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb);
return DISAS_GOTO_TB;
} else {
tcg_gen_movi_i64(psw_addr, dest);
@@ -1163,7 +1167,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
bool is_imm, int imm, TCGv_i64 cdest)
{
DisasJumpType ret;
- uint64_t dest = s->pc + 2 * imm;
+ uint64_t dest = s->base.pc_next + 2 * imm;
TCGLabel *lab;
/* Take care of the special cases first. */
@@ -1172,7 +1176,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
goto egress;
}
if (is_imm) {
- if (dest == s->next_pc) {
+ if (dest == s->pc_tmp) {
/* Branch to next. */
per_branch(s, true);
ret = DISAS_NEXT;
@@ -1196,7 +1200,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
}
}
- if (use_goto_tb(s, s->next_pc)) {
+ if (use_goto_tb(s, s->pc_tmp)) {
if (is_imm && use_goto_tb(s, dest)) {
/* Both exits can use goto_tb. */
update_cc_op(s);
@@ -1210,15 +1214,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
/* Branch not taken. */
tcg_gen_goto_tb(0);
- tcg_gen_movi_i64(psw_addr, s->next_pc);
- tcg_gen_exit_tb((uintptr_t)s->tb + 0);
+ tcg_gen_movi_i64(psw_addr, s->pc_tmp);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb + 0);
/* Branch taken. */
gen_set_label(lab);
per_breaking_event(s);
tcg_gen_goto_tb(1);
tcg_gen_movi_i64(psw_addr, dest);
- tcg_gen_exit_tb((uintptr_t)s->tb + 1);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb + 1);
ret = DISAS_GOTO_TB;
} else {
@@ -1240,8 +1244,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
/* Branch not taken. */
update_cc_op(s);
tcg_gen_goto_tb(0);
- tcg_gen_movi_i64(psw_addr, s->next_pc);
- tcg_gen_exit_tb((uintptr_t)s->tb + 0);
+ tcg_gen_movi_i64(psw_addr, s->pc_tmp);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb + 0);
gen_set_label(lab);
if (is_imm) {
@@ -1255,7 +1259,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
Most commonly we're single-stepping or some other condition that
disables all use of goto_tb. Just update the PC and exit. */
- TCGv_i64 next = tcg_const_i64(s->next_pc);
+ TCGv_i64 next = tcg_const_i64(s->pc_tmp);
if (is_imm) {
cdest = tcg_const_i64(dest);
}
@@ -1444,7 +1448,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
{
- tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
+ tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->pc_tmp));
if (o->in2) {
tcg_gen_mov_i64(psw_addr, o->in2);
per_branch(s, false);
@@ -1456,8 +1460,8 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
{
- tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
- return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
+ tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->pc_tmp));
+ return help_goto_direct(s, s->base.pc_next + 2 * get_field(s->fields, i2));
}
static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
@@ -1990,7 +1994,7 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
addr = get_address(s, 0, b2, d2);
t_r1 = tcg_const_i32(r1);
t_r3 = tcg_const_i32(r3);
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3);
} else {
gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
@@ -2008,7 +2012,7 @@ static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
int r3 = get_field(s->fields, r3);
TCGv_i32 t_r3 = tcg_const_i32(r3);
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->in1, o->in2);
} else {
gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2);
@@ -2968,7 +2972,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
TCGMemOp mop = s->insn->data;
/* In a parallel context, stop the world and single step. */
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
update_psw_addr(s);
update_cc_op(s);
gen_exception(EXCP_ATOMIC);
@@ -2990,7 +2994,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
{
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_lpq_parallel(o->out, cpu_env, o->in2);
} else {
gen_helper_lpq(o->out, cpu_env, o->in2);
@@ -3040,7 +3044,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
o->in2 = NULL;
o->g_in2 = false;
- switch (s->tb->flags & FLAG_MASK_ASC) {
+ switch (s->base.tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 0);
break;
@@ -3690,11 +3694,11 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
/* Bizarre but true, we check the address of the current insn for the
specification exception, not the next to be executed. Thus the PoO
documents that Bad Things Happen two bytes before the end. */
- if (s->pc & ~mask) {
+ if (s->base.pc_next & ~mask) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- s->next_pc &= mask;
+ s->pc_tmp &= mask;
tsam = tcg_const_i64(sam);
tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
@@ -4408,7 +4412,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
{
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out);
} else {
gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
@@ -4497,8 +4501,8 @@ static DisasJumpType op_tam(DisasContext *s, DisasOps *o)
{
int cc = 0;
- cc |= (s->tb->flags & FLAG_MASK_64) ? 2 : 0;
- cc |= (s->tb->flags & FLAG_MASK_32) ? 1 : 0;
+ cc |= (s->base.tb->flags & FLAG_MASK_64) ? 2 : 0;
+ cc |= (s->base.tb->flags & FLAG_MASK_32) ? 1 : 0;
gen_op_movi_cc(s, cc);
return DISAS_NEXT;
}
@@ -5598,7 +5602,7 @@ static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
{
- o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
+ o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(f, i2) * 2);
}
#define SPEC_in2_ri2 0
@@ -5881,7 +5885,7 @@ static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
DisasFields *f)
{
- uint64_t insn, pc = s->pc;
+ uint64_t insn, pc = s->base.pc_next;
int op, op2, ilen;
const DisasInsn *info;
@@ -5913,7 +5917,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
g_assert_not_reached();
}
}
- s->next_pc = s->pc + ilen;
+ s->pc_tmp = s->base.pc_next + ilen;
s->ilen = ilen;
/* We can't actually determine the insn format until we've looked up
@@ -5998,8 +6002,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
}
#ifndef CONFIG_USER_ONLY
- if (s->tb->flags & FLAG_MASK_PER) {
- TCGv_i64 addr = tcg_const_i64(s->pc);
+ if (s->base.tb->flags & FLAG_MASK_PER) {
+ TCGv_i64 addr = tcg_const_i64(s->base.pc_next);
gen_helper_per_ifetch(cpu_env, addr);
tcg_temp_free_i64(addr);
}
@@ -6093,10 +6097,10 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
}
#ifndef CONFIG_USER_ONLY
- if (s->tb->flags & FLAG_MASK_PER) {
+ if (s->base.tb->flags & FLAG_MASK_PER) {
/* An exception might be triggered, save PSW if not already done. */
if (ret == DISAS_NEXT || ret == DISAS_PC_STALE) {
- tcg_gen_movi_i64(psw_addr, s->next_pc);
+ tcg_gen_movi_i64(psw_addr, s->pc_tmp);
}
/* Call the helper to check for a possible PER exception. */
@@ -6105,7 +6109,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
#endif
/* Advance to the next instruction. */
- s->pc = s->next_pc;
+ s->base.pc_next = s->pc_tmp;
return ret;
}
@@ -6113,26 +6117,25 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUS390XState *env = cs->env_ptr;
DisasContext dc;
- target_ulong pc_start;
uint64_t next_page_start;
int num_insns, max_insns;
DisasJumpType status;
bool do_debug;
- pc_start = tb->pc;
-
+ dc.base.pc_first = tb->pc;
/* 31-bit mode */
if (!(tb->flags & FLAG_MASK_64)) {
- pc_start &= 0x7fffffff;
+ dc.base.pc_first &= 0x7fffffff;
}
+ dc.base.pc_next = dc.base.pc_first;
+ dc.base.tb = tb;
+ dc.base.singlestep_enabled = cs->singlestep_enabled;
- dc.tb = tb;
- dc.pc = pc_start;
dc.cc_op = CC_OP_DYNAMIC;
- dc.ex_value = tb->cs_base;
- do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
+ dc.ex_value = dc.base.tb->cs_base;
+ do_debug = cs->singlestep_enabled;
- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ next_page_start = (dc.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
max_insns = tb_cflags(tb) & CF_COUNT_MASK;
@@ -6146,17 +6149,17 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
gen_tb_start(tb);
do {
- tcg_gen_insn_start(dc.pc, dc.cc_op);
+ tcg_gen_insn_start(dc.base.pc_next, dc.cc_op);
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
+ if (unlikely(cpu_breakpoint_test(cs, dc.base.pc_next, BP_ANY))) {
status = DISAS_PC_STALE;
do_debug = true;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
- dc.pc += 2;
+ dc.base.pc_next += 2;
break;
}
@@ -6169,11 +6172,11 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
/* If we reach a page boundary, are single stepping,
or exhaust instruction count, stop generation. */
if (status == DISAS_NEXT
- && (dc.pc >= next_page_start
+ && (dc.base.pc_next >= next_page_start
|| tcg_op_buf_full()
|| num_insns >= max_insns
|| singlestep
- || cs->singlestep_enabled
+ || dc.base.singlestep_enabled
|| dc.ex_value)) {
status = DISAS_TOO_MANY;
}
@@ -6213,19 +6216,20 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
gen_tb_end(tb, num_insns);
- tb->size = dc.pc - pc_start;
+ tb->size = dc.base.pc_next - dc.base.pc_first;
tb->icount = num_insns;
#if defined(S390X_DEBUG_DISAS)
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
+ && qemu_log_in_addr_range(dc.base.pc_first)) {
qemu_log_lock();
if (unlikely(dc.ex_value)) {
/* ??? Unfortunately log_target_disas can't use host memory. */
qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value);
} else {
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc.pc - pc_start);
+ qemu_log("IN: %s\n", lookup_symbol(dc.base.pc_first));
+ log_target_disas(cs, dc.base.pc_first,
+ dc.base.pc_next - dc.base.pc_first);
qemu_log("\n");
}
qemu_log_unlock();
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase Emilio G. Cota
@ 2018-03-02 9:34 ` David Hildenbrand
2018-03-02 10:12 ` Cornelia Huck
1 sibling, 0 replies; 31+ messages in thread
From: David Hildenbrand @ 2018-03-02 9:34 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel
Cc: Richard Henderson, Cornelia Huck, Alexander Graf, qemu-s390x
On 01.03.2018 23:53, Emilio G. Cota wrote:
> Notes:
>
> - Did not convert {num,max}_insns and is_jmp, since the corresponding
> code will go away in the next patch.
>
> - Avoided a checkpatch error in use_exit_tb.
>
> - As suggested by David, (1) Drop ctx.pc and use
> ctx.base.pc_next instead, and (2) Rename ctx.next_pc to
> ctx.pc_tmp and add a comment about it.
>
> Suggested-by: David Hildenbrand <david@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Cornelia Huck <cohuck@redhat.com>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> target/s390x/translate.c | 146 ++++++++++++++++++++++++-----------------------
> 1 file changed, 75 insertions(+), 71 deletions(-)
>
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index 5346791..c83a57f 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -52,14 +52,18 @@ typedef struct DisasInsn DisasInsn;
> typedef struct DisasFields DisasFields;
>
> struct DisasContext {
> - struct TranslationBlock *tb;
> + DisasContextBase base;
> const DisasInsn *insn;
> DisasFields *fields;
> uint64_t ex_value;
> - uint64_t pc, next_pc;
> + /*
> + * During translate_one(), pc_tmp is used to determine the instruction
> + * to be executed after base.pc_next - e.g. next sequential instruction
> + * or a branch target.
> + */
> + uint64_t pc_tmp;
> uint32_t ilen;
> enum cc_op cc_op;
> - bool singlestep_enabled;
> };
>
> /* Information carried about a condition to be evaluated. */
> @@ -81,8 +85,8 @@ static uint64_t inline_branch_miss[CC_OP_MAX];
>
> static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
> {
> - if (!(s->tb->flags & FLAG_MASK_64)) {
> - if (s->tb->flags & FLAG_MASK_32) {
> + if (!(s->base.tb->flags & FLAG_MASK_64)) {
> + if (s->base.tb->flags & FLAG_MASK_32) {
> return pc | 0x80000000;
> }
> }
> @@ -188,16 +192,16 @@ static void return_low128(TCGv_i64 dest)
> static void update_psw_addr(DisasContext *s)
> {
> /* psw.addr */
> - tcg_gen_movi_i64(psw_addr, s->pc);
> + tcg_gen_movi_i64(psw_addr, s->base.pc_next);
> }
>
> static void per_branch(DisasContext *s, bool to_next)
> {
> #ifndef CONFIG_USER_ONLY
> - tcg_gen_movi_i64(gbea, s->pc);
> + tcg_gen_movi_i64(gbea, s->base.pc_next);
>
> - if (s->tb->flags & FLAG_MASK_PER) {
> - TCGv_i64 next_pc = to_next ? tcg_const_i64(s->next_pc) : psw_addr;
> + if (s->base.tb->flags & FLAG_MASK_PER) {
> + TCGv_i64 next_pc = to_next ? tcg_const_i64(s->pc_tmp) : psw_addr;
> gen_helper_per_branch(cpu_env, gbea, next_pc);
> if (to_next) {
> tcg_temp_free_i64(next_pc);
> @@ -210,16 +214,16 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
> TCGv_i64 arg1, TCGv_i64 arg2)
> {
> #ifndef CONFIG_USER_ONLY
> - if (s->tb->flags & FLAG_MASK_PER) {
> + if (s->base.tb->flags & FLAG_MASK_PER) {
> TCGLabel *lab = gen_new_label();
> tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab);
>
> - tcg_gen_movi_i64(gbea, s->pc);
> + tcg_gen_movi_i64(gbea, s->base.pc_next);
> gen_helper_per_branch(cpu_env, gbea, psw_addr);
>
> gen_set_label(lab);
> } else {
> - TCGv_i64 pc = tcg_const_i64(s->pc);
> + TCGv_i64 pc = tcg_const_i64(s->base.pc_next);
> tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc);
> tcg_temp_free_i64(pc);
> }
> @@ -228,7 +232,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
>
> static void per_breaking_event(DisasContext *s)
> {
> - tcg_gen_movi_i64(gbea, s->pc);
> + tcg_gen_movi_i64(gbea, s->base.pc_next);
> }
>
> static void update_cc_op(DisasContext *s)
> @@ -250,7 +254,7 @@ static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
>
> static int get_mem_index(DisasContext *s)
> {
> - switch (s->tb->flags & FLAG_MASK_ASC) {
> + switch (s->base.tb->flags & FLAG_MASK_ASC) {
> case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
> return 0;
> case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
> @@ -315,7 +319,7 @@ static inline void gen_trap(DisasContext *s)
> #ifndef CONFIG_USER_ONLY
> static void check_privileged(DisasContext *s)
> {
> - if (s->tb->flags & FLAG_MASK_PSTATE) {
> + if (s->base.tb->flags & FLAG_MASK_PSTATE) {
> gen_program_exception(s, PGM_PRIVILEGED);
> }
> }
> @@ -324,7 +328,7 @@ static void check_privileged(DisasContext *s)
> static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
> {
> TCGv_i64 tmp = tcg_temp_new_i64();
> - bool need_31 = !(s->tb->flags & FLAG_MASK_64);
> + bool need_31 = !(s->base.tb->flags & FLAG_MASK_64);
>
> /* Note that d2 is limited to 20 bits, signed. If we crop negative
> displacements early we create larger immedate addends. */
> @@ -537,9 +541,9 @@ static void gen_op_calc_cc(DisasContext *s)
>
> static bool use_exit_tb(DisasContext *s)
> {
> - return (s->singlestep_enabled ||
> - (tb_cflags(s->tb) & CF_LAST_IO) ||
> - (s->tb->flags & FLAG_MASK_PER));
> + return s->base.singlestep_enabled ||
> + (tb_cflags(s->base.tb) & CF_LAST_IO) ||
> + (s->base.tb->flags & FLAG_MASK_PER);
> }
>
> static bool use_goto_tb(DisasContext *s, uint64_t dest)
> @@ -548,8 +552,8 @@ static bool use_goto_tb(DisasContext *s, uint64_t dest)
> return false;
> }
> #ifndef CONFIG_USER_ONLY
> - return (dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) ||
> - (dest & TARGET_PAGE_MASK) == (s->pc & TARGET_PAGE_MASK);
> + return (dest & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) ||
> + (dest & TARGET_PAGE_MASK) == (s->base.pc_next & TARGET_PAGE_MASK);
> #else
> return true;
> #endif
> @@ -1141,7 +1145,7 @@ static void help_l2_shift(DisasContext *s, DisasFields *f,
>
> static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
> {
> - if (dest == s->next_pc) {
> + if (dest == s->pc_tmp) {
> per_branch(s, true);
> return DISAS_NEXT;
> }
> @@ -1150,7 +1154,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
> per_breaking_event(s);
> tcg_gen_goto_tb(0);
> tcg_gen_movi_i64(psw_addr, dest);
> - tcg_gen_exit_tb((uintptr_t)s->tb);
> + tcg_gen_exit_tb((uintptr_t)s->base.tb);
> return DISAS_GOTO_TB;
> } else {
> tcg_gen_movi_i64(psw_addr, dest);
> @@ -1163,7 +1167,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
> bool is_imm, int imm, TCGv_i64 cdest)
> {
> DisasJumpType ret;
> - uint64_t dest = s->pc + 2 * imm;
> + uint64_t dest = s->base.pc_next + 2 * imm;
> TCGLabel *lab;
>
> /* Take care of the special cases first. */
> @@ -1172,7 +1176,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
> goto egress;
> }
> if (is_imm) {
> - if (dest == s->next_pc) {
> + if (dest == s->pc_tmp) {
> /* Branch to next. */
> per_branch(s, true);
> ret = DISAS_NEXT;
> @@ -1196,7 +1200,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
> }
> }
>
> - if (use_goto_tb(s, s->next_pc)) {
> + if (use_goto_tb(s, s->pc_tmp)) {
> if (is_imm && use_goto_tb(s, dest)) {
> /* Both exits can use goto_tb. */
> update_cc_op(s);
> @@ -1210,15 +1214,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
>
> /* Branch not taken. */
> tcg_gen_goto_tb(0);
> - tcg_gen_movi_i64(psw_addr, s->next_pc);
> - tcg_gen_exit_tb((uintptr_t)s->tb + 0);
> + tcg_gen_movi_i64(psw_addr, s->pc_tmp);
> + tcg_gen_exit_tb((uintptr_t)s->base.tb + 0);
>
> /* Branch taken. */
> gen_set_label(lab);
> per_breaking_event(s);
> tcg_gen_goto_tb(1);
> tcg_gen_movi_i64(psw_addr, dest);
> - tcg_gen_exit_tb((uintptr_t)s->tb + 1);
> + tcg_gen_exit_tb((uintptr_t)s->base.tb + 1);
>
> ret = DISAS_GOTO_TB;
> } else {
> @@ -1240,8 +1244,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
> /* Branch not taken. */
> update_cc_op(s);
> tcg_gen_goto_tb(0);
> - tcg_gen_movi_i64(psw_addr, s->next_pc);
> - tcg_gen_exit_tb((uintptr_t)s->tb + 0);
> + tcg_gen_movi_i64(psw_addr, s->pc_tmp);
> + tcg_gen_exit_tb((uintptr_t)s->base.tb + 0);
>
> gen_set_label(lab);
> if (is_imm) {
> @@ -1255,7 +1259,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
> Most commonly we're single-stepping or some other condition that
> disables all use of goto_tb. Just update the PC and exit. */
>
> - TCGv_i64 next = tcg_const_i64(s->next_pc);
> + TCGv_i64 next = tcg_const_i64(s->pc_tmp);
> if (is_imm) {
> cdest = tcg_const_i64(dest);
> }
> @@ -1444,7 +1448,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
>
> static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
> {
> - tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
> + tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->pc_tmp));
> if (o->in2) {
> tcg_gen_mov_i64(psw_addr, o->in2);
> per_branch(s, false);
> @@ -1456,8 +1460,8 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
>
> static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
> {
> - tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
> - return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
> + tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->pc_tmp));
> + return help_goto_direct(s, s->base.pc_next + 2 * get_field(s->fields, i2));
> }
>
> static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
> @@ -1990,7 +1994,7 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
> addr = get_address(s, 0, b2, d2);
> t_r1 = tcg_const_i32(r1);
> t_r3 = tcg_const_i32(r3);
> - if (tb_cflags(s->tb) & CF_PARALLEL) {
> + if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3);
> } else {
> gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
> @@ -2008,7 +2012,7 @@ static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
> int r3 = get_field(s->fields, r3);
> TCGv_i32 t_r3 = tcg_const_i32(r3);
>
> - if (tb_cflags(s->tb) & CF_PARALLEL) {
> + if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->in1, o->in2);
> } else {
> gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2);
> @@ -2968,7 +2972,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
> TCGMemOp mop = s->insn->data;
>
> /* In a parallel context, stop the world and single step. */
> - if (tb_cflags(s->tb) & CF_PARALLEL) {
> + if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> update_psw_addr(s);
> update_cc_op(s);
> gen_exception(EXCP_ATOMIC);
> @@ -2990,7 +2994,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
>
> static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
> {
> - if (tb_cflags(s->tb) & CF_PARALLEL) {
> + if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> gen_helper_lpq_parallel(o->out, cpu_env, o->in2);
> } else {
> gen_helper_lpq(o->out, cpu_env, o->in2);
> @@ -3040,7 +3044,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
> o->in2 = NULL;
> o->g_in2 = false;
>
> - switch (s->tb->flags & FLAG_MASK_ASC) {
> + switch (s->base.tb->flags & FLAG_MASK_ASC) {
> case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
> tcg_gen_movi_i64(ar1, 0);
> break;
> @@ -3690,11 +3694,11 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
> /* Bizarre but true, we check the address of the current insn for the
> specification exception, not the next to be executed. Thus the PoO
> documents that Bad Things Happen two bytes before the end. */
> - if (s->pc & ~mask) {
> + if (s->base.pc_next & ~mask) {
> gen_program_exception(s, PGM_SPECIFICATION);
> return DISAS_NORETURN;
> }
> - s->next_pc &= mask;
> + s->pc_tmp &= mask;
>
> tsam = tcg_const_i64(sam);
> tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
> @@ -4408,7 +4412,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
>
> static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
> {
> - if (tb_cflags(s->tb) & CF_PARALLEL) {
> + if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out);
> } else {
> gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
> @@ -4497,8 +4501,8 @@ static DisasJumpType op_tam(DisasContext *s, DisasOps *o)
> {
> int cc = 0;
>
> - cc |= (s->tb->flags & FLAG_MASK_64) ? 2 : 0;
> - cc |= (s->tb->flags & FLAG_MASK_32) ? 1 : 0;
> + cc |= (s->base.tb->flags & FLAG_MASK_64) ? 2 : 0;
> + cc |= (s->base.tb->flags & FLAG_MASK_32) ? 1 : 0;
> gen_op_movi_cc(s, cc);
> return DISAS_NEXT;
> }
> @@ -5598,7 +5602,7 @@ static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
>
> static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
> {
> - o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
> + o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(f, i2) * 2);
> }
> #define SPEC_in2_ri2 0
>
> @@ -5881,7 +5885,7 @@ static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
> static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
> DisasFields *f)
> {
> - uint64_t insn, pc = s->pc;
> + uint64_t insn, pc = s->base.pc_next;
> int op, op2, ilen;
> const DisasInsn *info;
>
> @@ -5913,7 +5917,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
> g_assert_not_reached();
> }
> }
> - s->next_pc = s->pc + ilen;
> + s->pc_tmp = s->base.pc_next + ilen;
> s->ilen = ilen;
>
> /* We can't actually determine the insn format until we've looked up
> @@ -5998,8 +6002,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
> }
>
> #ifndef CONFIG_USER_ONLY
> - if (s->tb->flags & FLAG_MASK_PER) {
> - TCGv_i64 addr = tcg_const_i64(s->pc);
> + if (s->base.tb->flags & FLAG_MASK_PER) {
> + TCGv_i64 addr = tcg_const_i64(s->base.pc_next);
> gen_helper_per_ifetch(cpu_env, addr);
> tcg_temp_free_i64(addr);
> }
> @@ -6093,10 +6097,10 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
> }
>
> #ifndef CONFIG_USER_ONLY
> - if (s->tb->flags & FLAG_MASK_PER) {
> + if (s->base.tb->flags & FLAG_MASK_PER) {
> /* An exception might be triggered, save PSW if not already done. */
> if (ret == DISAS_NEXT || ret == DISAS_PC_STALE) {
> - tcg_gen_movi_i64(psw_addr, s->next_pc);
> + tcg_gen_movi_i64(psw_addr, s->pc_tmp);
> }
>
> /* Call the helper to check for a possible PER exception. */
> @@ -6105,7 +6109,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
> #endif
>
> /* Advance to the next instruction. */
> - s->pc = s->next_pc;
> + s->base.pc_next = s->pc_tmp;
> return ret;
> }
>
> @@ -6113,26 +6117,25 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> {
> CPUS390XState *env = cs->env_ptr;
> DisasContext dc;
> - target_ulong pc_start;
> uint64_t next_page_start;
> int num_insns, max_insns;
> DisasJumpType status;
> bool do_debug;
>
> - pc_start = tb->pc;
> -
> + dc.base.pc_first = tb->pc;
> /* 31-bit mode */
> if (!(tb->flags & FLAG_MASK_64)) {
> - pc_start &= 0x7fffffff;
> + dc.base.pc_first &= 0x7fffffff;
> }
> + dc.base.pc_next = dc.base.pc_first;
> + dc.base.tb = tb;
> + dc.base.singlestep_enabled = cs->singlestep_enabled;
>
> - dc.tb = tb;
> - dc.pc = pc_start;
> dc.cc_op = CC_OP_DYNAMIC;
> - dc.ex_value = tb->cs_base;
> - do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
> + dc.ex_value = dc.base.tb->cs_base;
> + do_debug = cs->singlestep_enabled;
>
> - next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> + next_page_start = (dc.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
>
> num_insns = 0;
> max_insns = tb_cflags(tb) & CF_COUNT_MASK;
> @@ -6146,17 +6149,17 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> gen_tb_start(tb);
>
> do {
> - tcg_gen_insn_start(dc.pc, dc.cc_op);
> + tcg_gen_insn_start(dc.base.pc_next, dc.cc_op);
> num_insns++;
>
> - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
> + if (unlikely(cpu_breakpoint_test(cs, dc.base.pc_next, BP_ANY))) {
> status = DISAS_PC_STALE;
> do_debug = true;
> /* The address covered by the breakpoint must be included in
> [tb->pc, tb->pc + tb->size) in order to for it to be
> properly cleared -- thus we increment the PC here so that
> the logic setting tb->size below does the right thing. */
> - dc.pc += 2;
> + dc.base.pc_next += 2;
> break;
> }
>
> @@ -6169,11 +6172,11 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> /* If we reach a page boundary, are single stepping,
> or exhaust instruction count, stop generation. */
> if (status == DISAS_NEXT
> - && (dc.pc >= next_page_start
> + && (dc.base.pc_next >= next_page_start
> || tcg_op_buf_full()
> || num_insns >= max_insns
> || singlestep
> - || cs->singlestep_enabled
> + || dc.base.singlestep_enabled
> || dc.ex_value)) {
> status = DISAS_TOO_MANY;
> }
> @@ -6213,19 +6216,20 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
>
> gen_tb_end(tb, num_insns);
>
> - tb->size = dc.pc - pc_start;
> + tb->size = dc.base.pc_next - dc.base.pc_first;
> tb->icount = num_insns;
>
> #if defined(S390X_DEBUG_DISAS)
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
> - && qemu_log_in_addr_range(pc_start)) {
> + && qemu_log_in_addr_range(dc.base.pc_first)) {
> qemu_log_lock();
> if (unlikely(dc.ex_value)) {
> /* ??? Unfortunately log_target_disas can't use host memory. */
> qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value);
> } else {
> - qemu_log("IN: %s\n", lookup_symbol(pc_start));
> - log_target_disas(cs, pc_start, dc.pc - pc_start);
> + qemu_log("IN: %s\n", lookup_symbol(dc.base.pc_first));
> + log_target_disas(cs, dc.base.pc_first,
> + dc.base.pc_next - dc.base.pc_first);
> qemu_log("\n");
> }
> qemu_log_unlock();
>
Nothing jumped at me :)
Thanks!
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase Emilio G. Cota
2018-03-02 9:34 ` David Hildenbrand
@ 2018-03-02 10:12 ` Cornelia Huck
1 sibling, 0 replies; 31+ messages in thread
From: Cornelia Huck @ 2018-03-02 10:12 UTC (permalink / raw)
To: Emilio G. Cota
Cc: qemu-devel, Richard Henderson, David Hildenbrand, Alexander Graf,
qemu-s390x
On Thu, 1 Mar 2018 17:53:55 -0500
"Emilio G. Cota" <cota@braap.org> wrote:
> Notes:
>
> - Did not convert {num,max}_insns and is_jmp, since the corresponding
> code will go away in the next patch.
>
> - Avoided a checkpatch error in use_exit_tb.
>
> - As suggested by David, (1) Drop ctx.pc and use
> ctx.base.pc_next instead, and (2) Rename ctx.next_pc to
> ctx.pc_tmp and add a comment about it.
>
> Suggested-by: David Hildenbrand <david@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Cornelia Huck <cohuck@redhat.com>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> target/s390x/translate.c | 146 ++++++++++++++++++++++++-----------------------
> 1 file changed, 75 insertions(+), 71 deletions(-)
Acked-by: Cornelia Huck <cohuck@redhat.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (10 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 11/14] target/s390x: convert to DisasContextBase Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-02 10:06 ` David Hildenbrand
2018-03-02 10:13 ` Cornelia Huck
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 13/14] target/openrisc: convert to DisasContextBase Emilio G. Cota
` (5 subsequent siblings)
17 siblings, 2 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, David Hildenbrand, Cornelia Huck,
Alexander Graf, qemu-s390x
Note: I looked into dropping dc->do_debug. However, I don't see
an easy way to do it given that TOO_MANY is also valid
when we just translate more than max_insns. Thus, the check
for do_debug in "case DISAS_PC_CC_UPDATED" would still need
additional state to know whether or not we came from
breakpoint_check.
Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: qemu-s390x@nongnu.org
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/s390x/translate.c | 162 +++++++++++++++++++++++------------------------
1 file changed, 80 insertions(+), 82 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index c83a57f..097009e 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -64,6 +64,7 @@ struct DisasContext {
uint64_t pc_tmp;
uint32_t ilen;
enum cc_op cc_op;
+ bool do_debug;
};
/* Information carried about a condition to be evaluated. */
@@ -6113,98 +6114,87 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
return ret;
}
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
- CPUS390XState *env = cs->env_ptr;
- DisasContext dc;
- uint64_t next_page_start;
- int num_insns, max_insns;
- DisasJumpType status;
- bool do_debug;
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- dc.base.pc_first = tb->pc;
/* 31-bit mode */
- if (!(tb->flags & FLAG_MASK_64)) {
- dc.base.pc_first &= 0x7fffffff;
+ if (!(dc->base.tb->flags & FLAG_MASK_64)) {
+ dc->base.pc_first &= 0x7fffffff;
+ dc->base.pc_next = dc->base.pc_first;
}
- dc.base.pc_next = dc.base.pc_first;
- dc.base.tb = tb;
- dc.base.singlestep_enabled = cs->singlestep_enabled;
- dc.cc_op = CC_OP_DYNAMIC;
- dc.ex_value = dc.base.tb->cs_base;
- do_debug = cs->singlestep_enabled;
+ dc->cc_op = CC_OP_DYNAMIC;
+ dc->ex_value = dc->base.tb->cs_base;
+ dc->do_debug = dc->base.singlestep_enabled;
+}
- next_page_start = (dc.base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
+{
+}
- num_insns = 0;
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
+static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- gen_tb_start(tb);
+ tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
+}
- do {
- tcg_gen_insn_start(dc.base.pc_next, dc.cc_op);
- num_insns++;
+static bool s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- if (unlikely(cpu_breakpoint_test(cs, dc.base.pc_next, BP_ANY))) {
- status = DISAS_PC_STALE;
- do_debug = true;
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- dc.base.pc_next += 2;
- break;
- }
+ dc->base.is_jmp = DISAS_PC_STALE;
+ dc->do_debug = true;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->base.pc_next += 2;
+ return true;
+}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ CPUS390XState *env = cs->env_ptr;
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- status = translate_one(env, &dc);
-
- /* If we reach a page boundary, are single stepping,
- or exhaust instruction count, stop generation. */
- if (status == DISAS_NEXT
- && (dc.base.pc_next >= next_page_start
- || tcg_op_buf_full()
- || num_insns >= max_insns
- || singlestep
- || dc.base.singlestep_enabled
- || dc.ex_value)) {
- status = DISAS_TOO_MANY;
- }
- } while (status == DISAS_NEXT);
+ dc->base.is_jmp = translate_one(env, dc);
+ if (dc->base.is_jmp == DISAS_NEXT) {
+ uint64_t next_page;
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
+ next_page = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ if (dc->base.pc_next >= next_page || dc->ex_value) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
+ }
}
+}
+
+static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- switch (status) {
+ switch (dc->base.is_jmp) {
case DISAS_GOTO_TB:
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
case DISAS_PC_STALE:
case DISAS_PC_STALE_NOCHAIN:
- update_psw_addr(&dc);
+ update_psw_addr(dc);
/* FALLTHRU */
case DISAS_PC_UPDATED:
/* Next TB starts off with CC_OP_DYNAMIC, so make sure the
cc op type is in env */
- update_cc_op(&dc);
+ update_cc_op(dc);
/* FALLTHRU */
case DISAS_PC_CC_UPDATED:
/* Exit the TB, either by raising a debug exception or by return. */
- if (do_debug) {
+ if (dc->do_debug) {
gen_exception(EXCP_DEBUG);
- } else if (use_exit_tb(&dc) || status == DISAS_PC_STALE_NOCHAIN) {
+ } else if (use_exit_tb(dc) ||
+ dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
tcg_gen_exit_tb(0);
} else {
tcg_gen_lookup_and_goto_ptr();
@@ -6213,28 +6203,36 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
default:
g_assert_not_reached();
}
+}
- gen_tb_end(tb, num_insns);
-
- tb->size = dc.base.pc_next - dc.base.pc_first;
- tb->icount = num_insns;
+static void s390x_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
-#if defined(S390X_DEBUG_DISAS)
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(dc.base.pc_first)) {
- qemu_log_lock();
- if (unlikely(dc.ex_value)) {
- /* ??? Unfortunately log_target_disas can't use host memory. */
- qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value);
- } else {
- qemu_log("IN: %s\n", lookup_symbol(dc.base.pc_first));
- log_target_disas(cs, dc.base.pc_first,
- dc.base.pc_next - dc.base.pc_first);
- qemu_log("\n");
- }
- qemu_log_unlock();
+ if (unlikely(dc->ex_value)) {
+ /* ??? Unfortunately log_target_disas can't use host memory. */
+ qemu_log("IN: EXECUTE %016" PRIx64, dc->ex_value);
+ } else {
+ qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
+ log_target_disas(cs, dc->base.pc_first, dc->base.tb->size);
}
-#endif
+}
+
+static const TranslatorOps s390x_tr_ops = {
+ .init_disas_context = s390x_tr_init_disas_context,
+ .tb_start = s390x_tr_tb_start,
+ .insn_start = s390x_tr_insn_start,
+ .breakpoint_check = s390x_tr_breakpoint_check,
+ .translate_insn = s390x_tr_translate_insn,
+ .tb_stop = s390x_tr_tb_stop,
+ .disas_log = s390x_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+{
+ DisasContext dc;
+
+ translator_loop(&s390x_tr_ops, &dc.base, cs, tb);
}
void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps Emilio G. Cota
@ 2018-03-02 10:06 ` David Hildenbrand
2018-03-02 10:13 ` Cornelia Huck
1 sibling, 0 replies; 31+ messages in thread
From: David Hildenbrand @ 2018-03-02 10:06 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel
Cc: Richard Henderson, Cornelia Huck, Alexander Graf, qemu-s390x
On 01.03.2018 23:53, Emilio G. Cota wrote:
> Note: I looked into dropping dc->do_debug. However, I don't see
> an easy way to do it given that TOO_MANY is also valid
> when we just translate more than max_insns. Thus, the check
> for do_debug in "case DISAS_PC_CC_UPDATED" would still need
> additional state to know whether or not we came from
> breakpoint_check.
Looks much cleaner! The do_debug() thing is fine for now.
> - if (unlikely(cpu_breakpoint_test(cs, dc.base.pc_next, BP_ANY))) {
> - status = DISAS_PC_STALE;
> - do_debug = true;
> - /* The address covered by the breakpoint must be included in
> - [tb->pc, tb->pc + tb->size) in order to for it to be
> - properly cleared -- thus we increment the PC here so that
> - the logic setting tb->size below does the right thing. */
> - dc.base.pc_next += 2;
> - break;
> - }
> + dc->base.is_jmp = DISAS_PC_STALE;
> + dc->do_debug = true;
> + /* The address covered by the breakpoint must be included in
> + [tb->pc, tb->pc + tb->size) in order to for it to be
> + properly cleared -- thus we increment the PC here so that
> + the logic setting tb->size below does the right thing. */
> + dc->base.pc_next += 2;
This comment is now wrong. ("the logic in translator_loop()" ?)
Reviewed-by: David Hildenbrand <david@redhat.com>
Gave this series a quick test:
kvm-unit-tests pass (you need to rebase to have all tests passing),
fedora 27 boots
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps Emilio G. Cota
2018-03-02 10:06 ` David Hildenbrand
@ 2018-03-02 10:13 ` Cornelia Huck
1 sibling, 0 replies; 31+ messages in thread
From: Cornelia Huck @ 2018-03-02 10:13 UTC (permalink / raw)
To: Emilio G. Cota
Cc: qemu-devel, Richard Henderson, David Hildenbrand, Alexander Graf,
qemu-s390x
On Thu, 1 Mar 2018 17:53:56 -0500
"Emilio G. Cota" <cota@braap.org> wrote:
> Note: I looked into dropping dc->do_debug. However, I don't see
> an easy way to do it given that TOO_MANY is also valid
> when we just translate more than max_insns. Thus, the check
> for do_debug in "case DISAS_PC_CC_UPDATED" would still need
> additional state to know whether or not we came from
> breakpoint_check.
>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Cornelia Huck <cohuck@redhat.com>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> target/s390x/translate.c | 162 +++++++++++++++++++++++------------------------
> 1 file changed, 80 insertions(+), 82 deletions(-)
Acked-by: Cornelia Huck <cohuck@redhat.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Qemu-devel] [PATCHv1 13/14] target/openrisc: convert to DisasContextBase
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (11 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 12/14] target/s390x: convert to TranslatorOps Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 14/14] target/openrisc: convert to TranslatorOps Emilio G. Cota
` (4 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Stafford Horne
While at it, set is_jmp to DISAS_NORETURN when generating
an exception.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/openrisc/translate.c | 93 ++++++++++++++++++++++-----------------------
1 file changed, 46 insertions(+), 47 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 2747b24..b37414f 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -36,7 +36,8 @@
#include "exec/log.h"
#define LOG_DIS(str, ...) \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__)
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \
+ ## __VA_ARGS__)
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
@@ -44,13 +45,10 @@
#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
typedef struct DisasContext {
- TranslationBlock *tb;
- target_ulong pc;
- uint32_t is_jmp;
+ DisasContextBase base;
uint32_t mem_idx;
uint32_t tb_flags;
uint32_t delayed_branch;
- bool singlestep_enabled;
} DisasContext;
static TCGv cpu_sr;
@@ -126,9 +124,9 @@ static void gen_exception(DisasContext *dc, unsigned int excp)
static void gen_illegal_exception(DisasContext *dc)
{
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_ILLEGAL);
- dc->is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_NORETURN;
}
/* not used yet, open it when we need or64. */
@@ -166,12 +164,12 @@ static void check_ov64s(DisasContext *dc)
static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
{
- if (unlikely(dc->singlestep_enabled)) {
+ if (unlikely(dc->base.singlestep_enabled)) {
return false;
}
#ifndef CONFIG_USER_ONLY
- return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+ return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
@@ -182,10 +180,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
if (use_goto_tb(dc, dest)) {
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_goto_tb(n);
- tcg_gen_exit_tb((uintptr_t)dc->tb + n);
+ tcg_gen_exit_tb((uintptr_t)dc->base.tb + n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
- if (dc->singlestep_enabled) {
+ if (dc->base.singlestep_enabled) {
gen_exception(dc, EXCP_DEBUG);
}
tcg_gen_exit_tb(0);
@@ -194,16 +192,16 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
{
- target_ulong tmp_pc = dc->pc + n26 * 4;
+ target_ulong tmp_pc = dc->base.pc_next + n26 * 4;
switch (op0) {
case 0x00: /* l.j */
tcg_gen_movi_tl(jmp_pc, tmp_pc);
break;
case 0x01: /* l.jal */
- tcg_gen_movi_tl(cpu_R[9], dc->pc + 8);
+ tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8);
/* Optimize jal being used to load the PC for PIC. */
- if (tmp_pc == dc->pc + 8) {
+ if (tmp_pc == dc->base.pc_next + 8) {
return;
}
tcg_gen_movi_tl(jmp_pc, tmp_pc);
@@ -211,7 +209,7 @@ static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
case 0x03: /* l.bnf */
case 0x04: /* l.bf */
{
- TCGv t_next = tcg_const_tl(dc->pc + 8);
+ TCGv t_next = tcg_const_tl(dc->base.pc_next + 8);
TCGv t_true = tcg_const_tl(tmp_pc);
TCGv t_zero = tcg_const_tl(0);
@@ -227,7 +225,7 @@ static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
break;
case 0x12: /* l.jalr */
- tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
+ tcg_gen_movi_tl(cpu_R[9], (dc->base.pc_next + 8));
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
break;
default:
@@ -795,7 +793,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
return;
}
gen_helper_rfe(cpu_env);
- dc->is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_UPDATE;
#endif
}
break;
@@ -1254,15 +1252,16 @@ static void dec_sys(DisasContext *dc, uint32_t insn)
switch (op0) {
case 0x000: /* l.sys */
LOG_DIS("l.sys %d\n", K16);
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_SYSCALL);
- dc->is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 0x100: /* l.trap */
LOG_DIS("l.trap %d\n", K16);
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_TRAP);
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 0x300: /* l.csync */
@@ -1479,7 +1478,7 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
{
uint32_t op0;
uint32_t insn;
- insn = cpu_ldl_code(&cpu->env, dc->pc);
+ insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
op0 = extract32(insn, 26, 6);
switch (op0) {
@@ -1532,14 +1531,15 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
int max_insns;
pc_start = tb->pc;
- dc->tb = tb;
- dc->is_jmp = DISAS_NEXT;
- dc->pc = pc_start;
+ dc->base.tb = tb;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+ dc->base.pc_next = pc_start;
+ dc->base.is_jmp = DISAS_NEXT;
+
dc->mem_idx = cpu_mmu_index(&cpu->env, false);
- dc->tb_flags = tb->flags;
+ dc->tb_flags = dc->base.tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
- dc->singlestep_enabled = cs->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
num_insns = 0;
@@ -1570,19 +1570,19 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
}
do {
- tcg_gen_insn_start(dc->pc, (dc->delayed_branch ? 1 : 0)
+ tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
| (num_insns ? 2 : 0));
num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_DEBUG);
- dc->is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_NORETURN;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
- dc->pc += 4;
+ dc->base.pc_next += 4;
break;
}
@@ -1590,7 +1590,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
gen_io_start();
}
disas_openrisc_insn(dc, cpu);
- dc->pc = dc->pc + 4;
+ dc->base.pc_next += 4;
/* delay slot */
if (dc->delayed_branch) {
@@ -1598,15 +1598,15 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (!dc->delayed_branch) {
tcg_gen_mov_tl(cpu_pc, jmp_pc);
tcg_gen_discard_tl(jmp_pc);
- dc->is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_UPDATE;
break;
}
}
- } while (!dc->is_jmp
+ } while (!dc->base.is_jmp
&& !tcg_op_buf_full()
- && !cs->singlestep_enabled
+ && !dc->base.singlestep_enabled
&& !singlestep
- && (dc->pc < next_page_start)
+ && (dc->base.pc_next < next_page_start)
&& num_insns < max_insns);
if (tb_cflags(tb) & CF_LAST_IO) {
@@ -1617,35 +1617,34 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
}
- tcg_gen_movi_tl(cpu_ppc, dc->pc - 4);
- if (dc->is_jmp == DISAS_NEXT) {
- dc->is_jmp = DISAS_UPDATE;
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
+ if (dc->base.is_jmp == DISAS_NEXT) {
+ dc->base.is_jmp = DISAS_UPDATE;
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
}
- if (unlikely(cs->singlestep_enabled)) {
+ if (unlikely(dc->base.singlestep_enabled)) {
gen_exception(dc, EXCP_DEBUG);
} else {
- switch (dc->is_jmp) {
+ switch (dc->base.is_jmp) {
case DISAS_NEXT:
- gen_goto_tb(dc, 0, dc->pc);
+ gen_goto_tb(dc, 0, dc->base.pc_next);
break;
default:
+ case DISAS_NORETURN:
case DISAS_JUMP:
+ case DISAS_TB_JUMP:
break;
case DISAS_UPDATE:
/* indicate that the hash table must be used
to find the next TB */
tcg_gen_exit_tb(0);
break;
- case DISAS_TB_JUMP:
- /* nothing more to generate */
- break;
}
}
gen_tb_end(tb, num_insns);
- tb->size = dc->pc - pc_start;
+ tb->size = dc->base.pc_next - pc_start;
tb->icount = num_insns;
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* [Qemu-devel] [PATCHv1 14/14] target/openrisc: convert to TranslatorOps
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (12 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 13/14] target/openrisc: convert to DisasContextBase Emilio G. Cota
@ 2018-03-01 22:53 ` Emilio G. Cota
2018-03-02 10:10 ` [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Cornelia Huck
` (3 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-01 22:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Stafford Horne
Notes:
- Changed the num_insns test in insn_start to check for
dc->base.num_insns > 1, since when tb_start is first
called in a TB, base.num_insns is already set to 1.
- Removed DISAS_NEXT from the switch in tb_stop; use
DISAS_TOO_MANY instead.
- Added an assert_not_reached on tb_stop for DISAS_NEXT
and the default case.
- Merged the two separate log_target_disas calls into the
disas_log op.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/openrisc/translate.c | 163 +++++++++++++++++++++-----------------------
1 file changed, 79 insertions(+), 84 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index b37414f..7cf29cd 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1520,46 +1520,22 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
}
}
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
{
+ DisasContext *dc = container_of(dcb, DisasContext, base);
CPUOpenRISCState *env = cs->env_ptr;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- struct DisasContext ctx, *dc = &ctx;
- uint32_t pc_start;
- uint32_t next_page_start;
- int num_insns;
- int max_insns;
-
- pc_start = tb->pc;
-
- dc->base.tb = tb;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
- dc->base.pc_next = pc_start;
- dc->base.is_jmp = DISAS_NEXT;
+ int bound;
- dc->mem_idx = cpu_mmu_index(&cpu->env, false);
+ dc->mem_idx = cpu_mmu_index(env, false);
dc->tb_flags = dc->base.tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
+ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
+}
- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- num_insns = 0;
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
-
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
-
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- qemu_log_lock();
- qemu_log("----------------\n");
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- }
-
- gen_tb_start(tb);
+static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
+{
+ DisasContext *dc = container_of(db, DisasContext, base);
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
@@ -1568,50 +1544,55 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
} else {
cpu_R[0] = cpu_R0;
}
+}
- do {
- tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
- | (num_insns ? 2 : 0));
- num_insns++;
+static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
- tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
- gen_exception(dc, EXCP_DEBUG);
- dc->base.is_jmp = DISAS_NORETURN;
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- dc->base.pc_next += 4;
- break;
- }
+ tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
+ | (dc->base.num_insns > 1 ? 2 : 0));
+}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
- disas_openrisc_insn(dc, cpu);
- dc->base.pc_next += 4;
-
- /* delay slot */
- if (dc->delayed_branch) {
- dc->delayed_branch--;
- if (!dc->delayed_branch) {
- tcg_gen_mov_tl(cpu_pc, jmp_pc);
- tcg_gen_discard_tl(jmp_pc);
- dc->base.is_jmp = DISAS_UPDATE;
- break;
- }
+static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
+ gen_exception(dc, EXCP_DEBUG);
+ dc->base.is_jmp = DISAS_NORETURN;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->base.pc_next += 4;
+ return true;
+}
+
+static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ disas_openrisc_insn(dc, cpu);
+ dc->base.pc_next += 4;
+
+ /* delay slot */
+ if (dc->delayed_branch) {
+ dc->delayed_branch--;
+ if (!dc->delayed_branch) {
+ tcg_gen_mov_tl(cpu_pc, jmp_pc);
+ tcg_gen_discard_tl(jmp_pc);
+ dc->base.is_jmp = DISAS_UPDATE;
+ return;
}
- } while (!dc->base.is_jmp
- && !tcg_op_buf_full()
- && !dc->base.singlestep_enabled
- && !singlestep
- && (dc->base.pc_next < next_page_start)
- && num_insns < max_insns);
-
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
}
+}
+
+static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
@@ -1626,10 +1607,9 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
gen_exception(dc, EXCP_DEBUG);
} else {
switch (dc->base.is_jmp) {
- case DISAS_NEXT:
+ case DISAS_TOO_MANY:
gen_goto_tb(dc, 0, dc->base.pc_next);
break;
- default:
case DISAS_NORETURN:
case DISAS_JUMP:
case DISAS_TB_JUMP:
@@ -1639,20 +1619,35 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
to find the next TB */
tcg_gen_exit_tb(0);
break;
+ default:
+ g_assert_not_reached();
}
}
+}
- gen_tb_end(tb, num_insns);
+static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *s = container_of(dcbase, DisasContext, base);
- tb->size = dc->base.pc_next - pc_start;
- tb->icount = num_insns;
+ qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first));
+ log_target_disas(cs, s->base.pc_first, s->base.tb->size);
+}
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- log_target_disas(cs, pc_start, tb->size);
- qemu_log("\n");
- qemu_log_unlock();
- }
+static const TranslatorOps openrisc_tr_ops = {
+ .init_disas_context = openrisc_tr_init_disas_context,
+ .tb_start = openrisc_tr_tb_start,
+ .insn_start = openrisc_tr_insn_start,
+ .breakpoint_check = openrisc_tr_breakpoint_check,
+ .translate_insn = openrisc_tr_translate_insn,
+ .tb_stop = openrisc_tr_tb_stop,
+ .disas_log = openrisc_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+{
+ DisasContext ctx;
+
+ translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb);
}
void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (13 preceding siblings ...)
2018-03-01 22:53 ` [Qemu-devel] [PATCHv1 14/14] target/openrisc: convert to TranslatorOps Emilio G. Cota
@ 2018-03-02 10:10 ` Cornelia Huck
2018-03-05 21:58 ` Mark Cave-Ayland
` (2 subsequent siblings)
17 siblings, 0 replies; 31+ messages in thread
From: Cornelia Huck @ 2018-03-02 10:10 UTC (permalink / raw)
To: Emilio G. Cota
Cc: qemu-devel, Richard Henderson, Alexander Graf, Artyom Tarasenko,
Aurelien Jarno, David Hildenbrand, Mark Cave-Ayland, qemu-s390x,
Stafford Horne, Yongbok Kim
On Thu, 1 Mar 2018 17:53:44 -0500
"Emilio G. Cota" <cota@braap.org> wrote:
> [ What is this all about? See this message:
> http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
>
> Merged the separate patchsets I sent in the last couple of weeks into
> one set. This will be easier to merge since it will avoid potential
> merge conflicts due to adding max_insns to dc->base.
So, the plan is to merge that as a series? I'll go ahead and ack the
s390x patches, then.
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (14 preceding siblings ...)
2018-03-02 10:10 ` [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Cornelia Huck
@ 2018-03-05 21:58 ` Mark Cave-Ayland
2018-03-05 22:43 ` Emilio G. Cota
2018-03-05 23:57 ` Michael Clark
2018-04-04 23:21 ` Emilio G. Cota
17 siblings, 1 reply; 31+ messages in thread
From: Mark Cave-Ayland @ 2018-03-05 21:58 UTC (permalink / raw)
To: Emilio G. Cota, qemu-devel
Cc: Richard Henderson, Alexander Graf, Artyom Tarasenko,
Aurelien Jarno, Cornelia Huck, David Hildenbrand, qemu-s390x,
Stafford Horne, Yongbok Kim
On 01/03/18 22:53, Emilio G. Cota wrote:
> [ What is this all about? See this message:
> http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
>
> Merged the separate patchsets I sent in the last couple of weeks into
> one set. This will be easier to merge since it will avoid potential
> merge conflicts due to adding max_insns to dc->base.
>
> Changes since sending the separate series for sh4/sparc/mips/s390x/openrisc:
> - Rebased on top of master (669743979)
> - Added R-b's
> - sh4: no changes since v3
> - mips: no changes (no reviews yet!)
> - sparc:
> + Use base.singlestep_enabled and singlestep like in other targets,
> e.g. Alpha.
> + Remove the unnecessary
> (dc.pc - pc_start) < (TARGET_PAGE_SIZE - 32))
> check.
> - s390x:
> + Remove dc->pc, use pc_next instead as David suggested.
> + Use dc for DisasContext instead of s.
> + Compute next_page in translate_insn instead of keeping it in dc.
> + Looked into dropping dc->do_debug, but don't see an easy way to do so.
> - openrisc:
> + Consistently use DISAS_NORETURN after generating an
> exception; fixed the two call sites that Richard pointed out,
> plus a couple of others that weren't visible in the previous patch.
> + Remove the dc->next_page_start field; instead, set the max_insn
> bound in translate_insn.
>
> You can fetch this series from:
> https://github.com/cota/qemu/tree/trloop-conv-v1
>
> Diffstat below.
>
> Thanks,
>
> Emilio
Hi Emilio,
I don't have enough knowledge of TCG internals to review this myself,
however I can run it through my complete set of OpenBIOS test images for
qemu-system-sparc and qemu-system-sparc64 if that helps?
ATB,
Mark.
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-05 21:58 ` Mark Cave-Ayland
@ 2018-03-05 22:43 ` Emilio G. Cota
2018-03-07 20:41 ` Mark Cave-Ayland
0 siblings, 1 reply; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-05 22:43 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: qemu-devel, Richard Henderson, Alexander Graf, Artyom Tarasenko,
Aurelien Jarno, Cornelia Huck, David Hildenbrand, qemu-s390x,
Stafford Horne, Yongbok Kim
On Mon, Mar 05, 2018 at 21:58:52 +0000, Mark Cave-Ayland wrote:
> I don't have enough knowledge of TCG internals to review this myself,
> however I can run it through my complete set of OpenBIOS test images for
> qemu-system-sparc and qemu-system-sparc64 if that helps?
That would be appreciated -- I only tested sparc64 by booting a NetBSD
guest.
Thanks,
Emilio
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-05 22:43 ` Emilio G. Cota
@ 2018-03-07 20:41 ` Mark Cave-Ayland
0 siblings, 0 replies; 31+ messages in thread
From: Mark Cave-Ayland @ 2018-03-07 20:41 UTC (permalink / raw)
To: Emilio G. Cota
Cc: David Hildenbrand, Cornelia Huck, Richard Henderson, qemu-devel,
Alexander Graf, qemu-s390x, Artyom Tarasenko, Stafford Horne,
Yongbok Kim, Aurelien Jarno
On 05/03/18 22:43, Emilio G. Cota wrote:
> On Mon, Mar 05, 2018 at 21:58:52 +0000, Mark Cave-Ayland wrote:
>> I don't have enough knowledge of TCG internals to review this myself,
>> however I can run it through my complete set of OpenBIOS test images for
>> qemu-system-sparc and qemu-system-sparc64 if that helps?
>
> That would be appreciated -- I only tested sparc64 by booting a NetBSD
> guest.
Hi Emilio,
I've given this a run through all my OpenBIOS test images for
qemu-system-sparc and qemu-system-sparc64 (including single-stepping via
gdb) and everything appears to be working fine using your trloop-conv-v1
branch.
Whilst I don't know enough about TCG to be able to review this patch,
for the sparc/sparc64 parts:
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
ATB,
Mark.
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (15 preceding siblings ...)
2018-03-05 21:58 ` Mark Cave-Ayland
@ 2018-03-05 23:57 ` Michael Clark
2018-03-06 2:56 ` Emilio G. Cota
2018-04-04 23:21 ` Emilio G. Cota
17 siblings, 1 reply; 31+ messages in thread
From: Michael Clark @ 2018-03-05 23:57 UTC (permalink / raw)
To: Emilio G. Cota
Cc: QEMU Developers, David Hildenbrand, Mark Cave-Ayland,
Cornelia Huck, Richard Henderson, Alexander Graf, qemu-s390x,
Artyom Tarasenko, Stafford Horne, Yongbok Kim, Aurelien Jarno
On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <cota@braap.org> wrote:
> [ What is this all about? See this message:
> http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
>
> Merged the separate patchsets I sent in the last couple of weeks into
> one set. This will be easier to merge since it will avoid potential
> merge conflicts due to adding max_insns to dc->base.
>
> Changes since sending the separate series for
> sh4/sparc/mips/s390x/openrisc:
> - Rebased on top of master (669743979)
> - Added R-b's
> - sh4: no changes since v3
> - mips: no changes (no reviews yet!)
> - sparc:
> + Use base.singlestep_enabled and singlestep like in other targets,
> e.g. Alpha.
> + Remove the unnecessary
> (dc.pc - pc_start) < (TARGET_PAGE_SIZE - 32))
> check.
> - s390x:
> + Remove dc->pc, use pc_next instead as David suggested.
> + Use dc for DisasContext instead of s.
> + Compute next_page in translate_insn instead of keeping it in dc.
> + Looked into dropping dc->do_debug, but don't see an easy way to do so.
> - openrisc:
> + Consistently use DISAS_NORETURN after generating an
> exception; fixed the two call sites that Richard pointed out,
> plus a couple of others that weren't visible in the previous patch.
> + Remove the dc->next_page_start field; instead, set the max_insn
> bound in translate_insn.
>
> You can fetch this series from:
> https://github.com/cota/qemu/tree/trloop-conv-v1
Curious to know what we would need to change in RISC-V translate.c:
-
https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c
I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
series against current QEMU master, and hopefully we get the RISC-V port
merged before the soft-freeze. Fingers crossed.
Diffstat below.
>
> Thanks,
>
> Emilio
>
> accel/tcg/translator.c | 21 +-
> include/exec/translator.h | 8 +-
> target/alpha/translate.c | 6 +-
> target/arm/translate-a64.c | 8 +-
> target/arm/translate.c | 9 +-
> target/hppa/translate.c | 7 +-
> target/i386/translate.c | 5 +-
> target/mips/translate.c | 623 +++++------
> target/openrisc/translate.c | 226 ++--
> target/ppc/translate.c | 5 +-
> target/s390x/translate.c | 1527 +++++++++++++--------------
> target/sh4/translate.c | 171 +--
> target/sparc/translate.c | 207 ++--
> 13 files changed, 1401 insertions(+), 1422 deletions(-)
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-05 23:57 ` Michael Clark
@ 2018-03-06 2:56 ` Emilio G. Cota
2018-03-06 3:40 ` Michael Clark
0 siblings, 1 reply; 31+ messages in thread
From: Emilio G. Cota @ 2018-03-06 2:56 UTC (permalink / raw)
To: Michael Clark
Cc: QEMU Developers, David Hildenbrand, Mark Cave-Ayland,
Cornelia Huck, Richard Henderson, Alexander Graf, qemu-s390x,
Artyom Tarasenko, Stafford Horne, Yongbok Kim, Aurelien Jarno
On Tue, Mar 06, 2018 at 12:57:13 +1300, Michael Clark wrote:
> On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <cota@braap.org> wrote:
>
> > [ What is this all about? See this message:
> > http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
(snip)
> > You can fetch this series from:
> > https://github.com/cota/qemu/tree/trloop-conv-v1
>
>
> Curious to know what we would need to change in RISC-V translate.c:
>
> -
> https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c
>
> I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
> series against current QEMU master, and hopefully we get the RISC-V port
> merged before the soft-freeze. Fingers crossed.
I have patches that convert riscv as well.
Once riscv is on master I'll send the patches to the list; I don't want
this work to delay the riscv merge even more!
Emilio
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-06 2:56 ` Emilio G. Cota
@ 2018-03-06 3:40 ` Michael Clark
0 siblings, 0 replies; 31+ messages in thread
From: Michael Clark @ 2018-03-06 3:40 UTC (permalink / raw)
To: Emilio G. Cota
Cc: Alexander Graf, Artyom Tarasenko, Aurelien Jarno, Cornelia Huck,
David Hildenbrand, Mark Cave-Ayland, QEMU Developers,
Richard Henderson, Stafford Horne, Yongbok Kim, qemu-s390x
On Tue, 6 Mar 2018 at 3:57 PM, Emilio G. Cota <cota@braap.org> wrote:
> On Tue, Mar 06, 2018 at 12:57:13 +1300, Michael Clark wrote:
> > On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <cota@braap.org> wrote:
> >
> > > [ What is this all about? See this message:
> > > http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
> (snip)
> > > You can fetch this series from:
> > > https://github.com/cota/qemu/tree/trloop-conv-v1
> >
> >
> > Curious to know what we would need to change in RISC-V translate.c:
> >
> > -
> >
> https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c
> >
> > I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
> > series against current QEMU master, and hopefully we get the RISC-V port
> > merged before the soft-freeze. Fingers crossed.
>
> I have patches that convert riscv as well.
>
> Once riscv is on master I'll send the patches to the list; I don't want
> this work to delay the riscv merge even more!
Appreciated. Thanks very much!
Michael
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets
2018-03-01 22:53 [Qemu-devel] [PATCHv1 00/14] Translation loop conversion for sh4/sparc/mips/s390x/openrisc targets Emilio G. Cota
` (16 preceding siblings ...)
2018-03-05 23:57 ` Michael Clark
@ 2018-04-04 23:21 ` Emilio G. Cota
17 siblings, 0 replies; 31+ messages in thread
From: Emilio G. Cota @ 2018-04-04 23:21 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Alexander Graf, Artyom Tarasenko,
Aurelien Jarno, Cornelia Huck, David Hildenbrand,
Mark Cave-Ayland, qemu-s390x, Stafford Horne, Yongbok Kim
On Thu, Mar 01, 2018 at 17:53:44 -0500, Emilio G. Cota wrote:
> [ What is this all about? See this message:
> http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
(snip)
> You can fetch this series from:
> https://github.com/cota/qemu/tree/trloop-conv-v1
*ping* on this series. A few patches are missing reviews, mostly mips/openrisc
bits.
Thanks,
Emilio
^ permalink raw reply [flat|nested] 31+ messages in thread