Re: [Qemu-devel] [PATCH v5 4/9] i386: Add new property to control cache info

[Eduardo Habkost <ehabkost@redhat.com>]

On Mon, Apr 09, 2018 at 07:51:24PM +0000, Moger, Babu wrote:
[...]
> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > index 67faa53..f4fbe3a 100644
> > > --- a/target/i386/cpu.c
> > > +++ b/target/i386/cpu.c
> > > @@ -5132,6 +5132,7 @@ static Property x86_cpu_properties[] = {
> > >                       false),
> > >      DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU,
> > vmware_cpuid_freq, true),
> > >      DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
> > > +    DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false),
> > 
> > I'm wondering the reason why Intel L1 caches aren't shared per threads,
> > L2 not shared per threads/cores etc? I mean, changing that will also
> > require new compat flag with very similar name.
> 
> I am not an expert on this topic. But, yes, If there is any future change in cache topology
> then it would require similar change. 

In the future I really hope we manage to represent cache
information in a more structured way, so other incompatible
changes could be represented by more descriptive options like
"l1-cache-size=N", "l2-sharing=cores", etc.

-- 
Eduardo