From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f5jbg-0006Dh-UL for qemu-devel@nongnu.org; Mon, 09 Apr 2018 23:06:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f5jbd-00023w-Lt for qemu-devel@nongnu.org; Mon, 09 Apr 2018 23:06:04 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:36867) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f5jbd-00021t-AC for qemu-devel@nongnu.org; Mon, 09 Apr 2018 23:06:01 -0400 Received: by mail-lf0-x242.google.com with SMTP id m200-v6so9485553lfm.4 for ; Mon, 09 Apr 2018 20:06:00 -0700 (PDT) Date: Tue, 10 Apr 2018 06:21:57 +0300 From: Antony Pavlov Message-Id: <20180410062157.0f5876180d0ff5c89dd80393@gmail.com> In-Reply-To: <1519998711-73430-20-git-send-email-mjc@sifive.com> References: <1519998711-73430-1-git-send-email-mjc@sifive.com> <1519998711-73430-20-git-send-email-mjc@sifive.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Clark Cc: qemu-devel@nongnu.org, Stefan O'Rear , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , RISC-V Patches On Sat, 3 Mar 2018 02:51:47 +1300 Michael Clark wrote: > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > BBL supports the SiFive UART for early console access via the SBI > (Supervisor Binary Interface) and the linux kernel SBI console. >=20 > The SiFive UART implements the pre qom legacy interface consistent > with the 16550a UART in 'hw/char/serial.c'. >=20 > Acked-by: Richard Henderson > Signed-off-by: Stefan O'Rear > Signed-off-by: Palmer Dabbelt > Signed-off-by: Michael Clark > --- > hw/riscv/sifive_uart.c | 176 +++++++++++++++++++++++++++++++++++= ++++++ > include/hw/riscv/sifive_uart.h | 71 +++++++++++++++++ > 2 files changed, 247 insertions(+) > create mode 100644 hw/riscv/sifive_uart.c > create mode 100644 include/hw/riscv/sifive_uart.h >=20 > diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c > new file mode 100644 > index 0000000..b0c3798 > --- /dev/null > +++ b/hw/riscv/sifive_uart.c > @@ -0,0 +1,176 @@ > +/* > + * QEMU model of the UART on the SiFive E300 and U500 series SOCs. > + * > + * Copyright (c) 2016 Stefan O'Rear > + * > + * This program is free software; you can redistribute it and/or modify = it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License= for > + * more details. > + * > + * You should have received a copy of the GNU General Public License alo= ng with > + * this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "hw/sysbus.h" > +#include "chardev/char.h" > +#include "chardev/char-fe.h" > +#include "target/riscv/cpu.h" > +#include "hw/riscv/sifive_uart.h" > > +/* > + * Not yet implemented: > + * > + * Transmit FIFO using "qemu/fifo8.h" > + * SIFIVE_UART_IE_TXWM interrupts > + * SIFIVE_UART_IE_RXWM interrupts must honor fifo watermark > + * Rx FIFO watermark interrupt trigger threshold > + * Tx FIFO watermark interrupt trigger threshold. > + */ > + > +static void update_irq(SiFiveUARTState *s) > +{ > + int cond =3D 0; > + if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { > + cond =3D 1; > + } > + if (cond) { > + qemu_irq_raise(s->irq); > + } else { > + qemu_irq_lower(s->irq); > + } > +} > + > +static uint64_t > +uart_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + SiFiveUARTState *s =3D opaque; > + unsigned char r; > + switch (addr) { > + case SIFIVE_UART_RXFIFO: > + if (s->rx_fifo_len) { > + r =3D s->rx_fifo[0]; > + memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); > + s->rx_fifo_len--; > + qemu_chr_fe_accept_input(&s->chr); > + update_irq(s); > + return r; > + } > + return 0x80000000; > + > + case SIFIVE_UART_TXFIFO: > + return 0; /* Should check tx fifo */ > + case SIFIVE_UART_IE: > + return s->ie; > + case SIFIVE_UART_IP: > + return s->rx_fifo_len ? SIFIVE_UART_IP_RXWM : 0; > + case SIFIVE_UART_TXCTRL: > + return s->txctrl; > + case SIFIVE_UART_RXCTRL: > + return s->rxctrl; > + case SIFIVE_UART_DIV: > + return s->div; > + } > + > + hw_error("%s: bad read: addr=3D0x%x\n", > + __func__, (int)addr); > + return 0; > +} > + > +static void > +uart_write(void *opaque, hwaddr addr, > + uint64_t val64, unsigned int size) > +{ > + SiFiveUARTState *s =3D opaque; > + uint32_t value =3D val64; > + unsigned char ch =3D value; > + > + switch (addr) { > + case SIFIVE_UART_TXFIFO: > + qemu_chr_fe_write(&s->chr, &ch, 1); > + return; > + case SIFIVE_UART_IE: > + s->ie =3D val64; > + update_irq(s); > + return; > + case SIFIVE_UART_TXCTRL: > + s->txctrl =3D val64; > + return; > + case SIFIVE_UART_RXCTRL: > + s->rxctrl =3D val64; > + return; > + case SIFIVE_UART_DIV: > + s->div =3D val64; > + return; > + } > + hw_error("%s: bad write: addr=3D0x%x v=3D0x%x\n", > + __func__, (int)addr, (int)value); > +} > + > +static const MemoryRegionOps uart_ops =3D { > + .read =3D uart_read, > + .write =3D uart_write, > + .endianness =3D DEVICE_NATIVE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 4, > + .max_access_size =3D 4 > + } > +}; > + > +static void uart_rx(void *opaque, const uint8_t *buf, int size) > +{ > + SiFiveUARTState *s =3D opaque; > + > + /* Got a byte. */ > + if (s->rx_fifo_len >=3D sizeof(s->rx_fifo)) { > + printf("WARNING: UART dropped char.\n"); > + return; > + } > + s->rx_fifo[s->rx_fifo_len++] =3D *buf; > + > + update_irq(s); > +} > + > +static int uart_can_rx(void *opaque) > +{ > + SiFiveUARTState *s =3D opaque; > + > + return s->rx_fifo_len < sizeof(s->rx_fifo); > +} > + > +static void uart_event(void *opaque, int event) > +{ > +} > + > +static int uart_be_change(void *opaque) > +{ > + SiFiveUARTState *s =3D opaque; > + > + qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, > + uart_be_change, s, NULL, true); > + > + return 0; > +} > + > +/* > + * Create UART device. > + */ > +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr = base, > + Chardev *chr, qemu_irq irq) > +{ > + SiFiveUARTState *s =3D g_malloc0(sizeof(SiFiveUARTState)); > + s->irq =3D irq; > + qemu_chr_fe_init(&s->chr, chr, &error_abort); > + qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, > + uart_be_change, s, NULL, true); > + memory_region_init_io(&s->mmio, NULL, &uart_ops, s, > + TYPE_SIFIVE_UART, SIFIVE_UART_MAX); > + memory_region_add_subregion(address_space, base, &s->mmio); > + return s; > +} > diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uar= t.h > new file mode 100644 > index 0000000..504f18a > --- /dev/null > +++ b/include/hw/riscv/sifive_uart.h > @@ -0,0 +1,71 @@ > +/* > + * SiFive UART interface > + * > + * Copyright (c) 2016 Stefan O'Rear > + * Copyright (c) 2017 SiFive, Inc. > + * > + * This program is free software; you can redistribute it and/or modify = it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License= for > + * more details. > + * > + * You should have received a copy of the GNU General Public License alo= ng with > + * this program. If not, see . > + */ > + > +#ifndef HW_SIFIVE_UART_H > +#define HW_SIFIVE_UART_H > + > +enum { > + SIFIVE_UART_TXFIFO =3D 0, > + SIFIVE_UART_RXFIFO =3D 4, > + SIFIVE_UART_TXCTRL =3D 8, > + SIFIVE_UART_TXMARK =3D 10, > + SIFIVE_UART_RXCTRL =3D 12, > + SIFIVE_UART_RXMARK =3D 14, > + SIFIVE_UART_IE =3D 16, > + SIFIVE_UART_IP =3D 20, > + SIFIVE_UART_DIV =3D 24, > + SIFIVE_UART_MAX =3D 32 > +}; > + > +enum { > + SIFIVE_UART_IE_TXWM =3D 1, /* Transmit watermark interrupt ena= ble */ > + SIFIVE_UART_IE_RXWM =3D 2 /* Receive watermark interrupt enab= le */ > +}; > + > +enum { > + SIFIVE_UART_IP_TXWM =3D 1, /* Transmit watermark interrupt pen= ding */ > + SIFIVE_UART_IP_RXWM =3D 2 /* Receive watermark interrupt pend= ing */ > +}; > + > +#define TYPE_SIFIVE_UART "riscv.sifive.uart" > + > +#define SIFIVE_UART(obj) \ > + OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART) > + > +typedef struct SiFiveUARTState { > + /*< private >*/ > + SysBusDevice parent_obj; You use SysBusDevive in this header file but there is no 'include "hw/sysbu= s.h"' in the header file itself. Please see my comment https://github.com/riscv/riscv-qemu/pull/130#issuecom= ment-379640538 > + /*< public >*/ > + qemu_irq irq; > + MemoryRegion mmio; > + CharBackend chr; Just the same thing. CharBackend is defined in "chardev/char-fe.h" please i= nclude it. > + uint8_t rx_fifo[8]; > + unsigned int rx_fifo_len; > + uint32_t ie; > + uint32_t ip; > + uint32_t txctrl; > + uint32_t rxctrl; > + uint32_t div; > +} SiFiveUARTState; > + > +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr = base, > + Chardev *chr, qemu_irq irq); > + > +#endif > --=20 > 2.7.0 >=20 >=20 --=20 Best regards, =A0 Antony Pavlov