From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44935) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8SQ0-00028e-Nb for qemu-devel@nongnu.org; Tue, 17 Apr 2018 11:21:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f8SPz-000286-SL for qemu-devel@nongnu.org; Tue, 17 Apr 2018 11:21:16 -0400 Date: Tue, 17 Apr 2018 11:21:01 -0400 From: Aaron Lindsay Message-ID: <20180417152101.GP24561@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> <1521232280-13089-13-git-send-email-alindsay@codeaurora.org> <20180412173625.GK24561@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180412173625.GK24561@codeaurora.org> Subject: Re: [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm , Alistair Francis , Wei Huang , Peter Crosthwaite , QEMU Developers , Michael Spradling , Digant Desai On Apr 12 13:36, Aaron Lindsay wrote: > On Apr 12 18:15, Peter Maydell wrote: > > On 16 March 2018 at 20:31, Aaron Lindsay wrote: > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > > index b0ef727..9c3b5ef 100644 > > > --- a/target/arm/cpu.h > > > +++ b/target/arm/cpu.h > > > @@ -458,6 +458,11 @@ typedef struct CPUARMState { > > > * was reset. Otherwise it stores the counter value > > > */ > > > uint64_t c15_ccnt; > > > + /* ccnt_cached_cycles is used to hold the last cycle count when > > > + * c15_ccnt holds the guest-visible count instead of the delta during > > > + * PMU operations which require this. > > > + */ > > > + uint64_t ccnt_cached_cycles; > > > > Can this ever hold valid state at a point when we need to do VM > > migration, or is it purely temporary ? > > I believe that as of this version of the patch it is temporary and will > not need to be migrated. However, I believe it's going to be necessary > to have two variables to represent the state of each counter in order to > implement interrupt on overflow. Coming back around to this, I don't see a way around using two variables to hold PMCCNTR's full state to make interrupt on overflow work. I haven't been able to find other examples or documentation covering state needing to be updated in more than one location for a given CP register - do you know of any I've missed or have recommendations about how to approach this? -Aaron -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.