From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	sai.pavan.boddu@xilinx.com, alistair@alistair23.me,
	frasse.iglesias@gmail.com, edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PATCH v2 2/5] target-microblaze: Fix trap checks for FPU insns
Date: Mon, 23 Apr 2018 14:32:22 +0200	[thread overview]
Message-ID: <20180423123225.30503-3-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20180423123225.30503-1-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Fix trap checks for FPU insns when extended FPU insns are enabled.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index f739751930..ec12fed49d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-          && (dc->cpu->cfg.use_fpu != 1)) {
+          && !dc->cpu->cfg.use_fpu) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
         return;
-- 
2.14.1
next prev parent reply	other threads:[~2018-04-23 12:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-23 12:32 [Qemu-devel] [PATCH v2 0/5] target-microblaze: Misc bug fixes Edgar E. Iglesias
2018-04-23 12:32 ` [Qemu-devel] [PATCH v2 1/5] target-microblaze: Respect MSR.PVR as read-only Edgar E. Iglesias
2018-04-23 19:29   ` Richard Henderson
2018-04-23 12:32 ` Edgar E. Iglesias [this message]
2018-04-23 19:29   ` [Qemu-devel] [PATCH v2 2/5] target-microblaze: Fix trap checks for FPU insns Richard Henderson
2018-04-23 12:32 ` [Qemu-devel] [PATCH v2 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed Edgar E. Iglesias
2018-04-23 19:31   ` Richard Henderson
2018-04-23 12:32 ` [Qemu-devel] [PATCH v2 4/5] target-microblaze: mmu: Make TLBSX write-only Edgar E. Iglesias
2018-04-23 19:32   ` Richard Henderson
2018-04-23 12:32 ` [Qemu-devel] [PATCH v2 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only Edgar E. Iglesias
2018-04-23 19:33   ` Richard Henderson
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