From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: [Qemu-devel] [PATCH v3 02/35] ppc/xive: add support for the LSI interrupt sources
Date: Tue, 24 Apr 2018 16:41:19 +1000 [thread overview]
Message-ID: <20180424064119.GO19804@umbus.fritz.box> (raw)
In-Reply-To: <ac69df02-8ee8-0506-36ac-83fdaccdca77@kaod.org>
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On Mon, Apr 23, 2018 at 09:31:24AM +0200, Cédric Le Goater wrote:
> On 04/23/2018 08:44 AM, David Gibson wrote:
> > On Thu, Apr 19, 2018 at 02:42:58PM +0200, Cédric Le Goater wrote:
> >> The 'sent' status of the LSI interrupt source is modeled with the 'P'
> >> bit of the ESB and the assertion status of the source is maintained in
> >> an array under the main sPAPRXive object. The type of the source is
> >> stored in the same array for practical reasons.
> >>
> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >> ---
> >> hw/intc/xive.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++----
> >> include/hw/ppc/xive.h | 16 +++++++++++++++
> >> 2 files changed, 66 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> >> index c70578759d02..060976077dd7 100644
> >> --- a/hw/intc/xive.c
> >> +++ b/hw/intc/xive.c
> >> @@ -104,6 +104,21 @@ static void xive_source_notify(XiveSource *xsrc, int srcno)
> >>
> >> }
> >>
> >> +/*
> >> + * LSI interrupt sources use the P bit and a custom assertion flag
> >> + */
> >> +static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno)
> >> +{
> >> + uint8_t old_pq = xive_source_pq_get(xsrc, srcno);
> >> +
> >> + if (old_pq == XIVE_ESB_RESET &&
> >> + xsrc->status[srcno] & XIVE_STATUS_ASSERTED) {
> >> + xive_source_pq_set(xsrc, srcno, XIVE_ESB_PENDING);
> >> + return true;
> >> + }
> >> + return false;
> >> +}
> >> +
> >> /* In a two pages ESB MMIO setting, even page is the trigger page, odd
> >> * page is for management */
> >> static inline bool xive_source_is_trigger_page(hwaddr addr)
> >> @@ -133,6 +148,13 @@ static uint64_t xive_source_esb_read(void *opaque, hwaddr addr, unsigned size)
> >> */
> >> ret = xive_source_pq_eoi(xsrc, srcno);
> >>
> >> + /* If the LSI source is still asserted, forward a new source
> >> + * event notification */
> >> + if (xive_source_irq_is_lsi(xsrc, srcno)) {
> >> + if (xive_source_lsi_trigger(xsrc, srcno)) {
> >> + xive_source_notify(xsrc, srcno);
> >> + }
> >> + }
> >> break;
> >>
> >> case XIVE_ESB_GET:
> >> @@ -183,6 +205,14 @@ static void xive_source_esb_write(void *opaque, hwaddr addr,
> >> * notification
> >> */
> >> notify = xive_source_pq_eoi(xsrc, srcno);
> >> +
> >> + /* LSI sources do not set the Q bit but they can still be
> >> + * asserted, in which case we should forward a new source
> >> + * event notification
> >> + */
> >> + if (xive_source_irq_is_lsi(xsrc, srcno)) {
> >> + notify = xive_source_lsi_trigger(xsrc, srcno);
> >> + }
>
> FYI, I have moved that common test under xive_source_pq_eoi()
Ok.
> >> break;
> >>
> >> default:
> >> @@ -216,8 +246,17 @@ static void xive_source_set_irq(void *opaque, int srcno, int val)
> >> XiveSource *xsrc = XIVE_SOURCE(opaque);
> >> bool notify = false;
> >>
> >> - if (val) {
> >> - notify = xive_source_pq_trigger(xsrc, srcno);
> >> + if (xive_source_irq_is_lsi(xsrc, srcno)) {
> >> + if (val) {
> >> + xsrc->status[srcno] |= XIVE_STATUS_ASSERTED;
> >> + } else {
> >> + xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED;
> >> + }
> >> + notify = xive_source_lsi_trigger(xsrc, srcno);
> >> + } else {
> >> + if (val) {
> >> + notify = xive_source_pq_trigger(xsrc, srcno);
> >> + }
> >> }
> >>
> >> /* Forward the source event notification for routing */
> >> @@ -234,13 +273,13 @@ void xive_source_pic_print_info(XiveSource *xsrc, Monitor *mon)
> >> xsrc->offset, xsrc->offset + xsrc->nr_irqs - 1);
> >> for (i = 0; i < xsrc->nr_irqs; i++) {
> >> uint8_t pq = xive_source_pq_get(xsrc, i);
> >> - uint32_t lisn = i + xsrc->offset;
> >>
> >> if (pq == XIVE_ESB_OFF) {
> >> continue;
> >> }
> >>
> >> - monitor_printf(mon, " %4x %c%c\n", lisn,
> >> + monitor_printf(mon, " %4x %s %c%c\n", i + xsrc->offset,
> >> + xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
> >> pq & XIVE_ESB_VAL_P ? 'P' : '-',
> >> pq & XIVE_ESB_VAL_Q ? 'Q' : '-');
> >> }
> >> @@ -249,6 +288,12 @@ void xive_source_pic_print_info(XiveSource *xsrc, Monitor *mon)
> >> static void xive_source_reset(DeviceState *dev)
> >> {
> >> XiveSource *xsrc = XIVE_SOURCE(dev);
> >> + int i;
> >> +
> >> + /* Keep the IRQ type */
> >> + for (i = 0; i < xsrc->nr_irqs; i++) {
> >> + xsrc->status[i] &= ~XIVE_STATUS_ASSERTED;
> >> + }
> >>
> >> /* SBEs are initialized to 0b01 which corresponds to "ints off" */
> >> memset(xsrc->sbe, 0x55, xsrc->sbe_size);
> >> @@ -273,6 +318,7 @@ static void xive_source_realize(DeviceState *dev, Error **errp)
> >>
> >> xsrc->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc,
> >> xsrc->nr_irqs);
> >> + xsrc->status = g_malloc0(xsrc->nr_irqs);
> >>
> >> /* Allocate the SBEs (State Bit Entry). 2 bits, so 4 entries per byte */
> >> xsrc->sbe_size = DIV_ROUND_UP(xsrc->nr_irqs, 4);
> >> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> >> index d92a50519edf..0b76dd278d9b 100644
> >> --- a/include/hw/ppc/xive.h
> >> +++ b/include/hw/ppc/xive.h
> >> @@ -33,6 +33,9 @@ typedef struct XiveSource {
> >> uint32_t nr_irqs;
> >> uint32_t offset;
> >> qemu_irq *qirqs;
> >> +#define XIVE_STATUS_LSI 0x1
> >> +#define XIVE_STATUS_ASSERTED 0x2
> >> + uint8_t *status;
> >
> > I don't love the idea of mixing configuration information (STATUS_LSI)
> > with runtime state information (ASSERTED) in the same field. Any
> > reason not to have these as parallel bitmaps.
>
> none. I can change that.
Ok.
> > Come to that.. is there a compelling reason to allow any individual
> > irq to be marked LSI or MSI, rather than using separate XiveSource
> > objects for MSIs and LSIs?
>
> yes. I would have preferred two distinct interrupt source objects but
> this is to be compatible with XICS, which uses only one. If we want
> to be able to change interrupt mode, the IRQ number space should be
> organized in the exact same way. Or we should change XICS also.
>
> Also, the change (a bitmap) is really small.
Hrm, but since XIVE supports thousands of irqs, it could be quite a
large bitmap.
It's not impossible - in fact, not really even that hard - to change
the existing irq layout on xics. It does need a new machine type
variant, of course.
> >> /* PQ bits */
> >> uint8_t *sbe;
> >
> > .. and come to that is there a reason to keep the ASSERTED bit in a
> > separate array from sbe? AFAICT the actual 2-bit-per-irq layout is
> > never exposed to the guests.
>
> indeed. we always use the xive_source_pq_get/set() helpers to
> manipulate the PQ bits. So we could add an extra bit for the ASSERT
> without too much changes. Could also we put the type there or would
> you still prefer a bitmap ?
I'd prefer the type (config information) be separate from the P, Q,
ASSERTED bits (state information).
> > Or, even re-use the Q bit for asserted in LSIs (but report it as
> > always 0 in the register read/write path).
>
> I would prefer to add extra status bits. It is easier to debug.
>
> Thanks,
>
> C.
>
> >> @@ -127,4 +130,17 @@ uint8_t xive_source_pq_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
> >>
> >> void xive_source_pic_print_info(XiveSource *xsrc, Monitor *mon);
> >>
> >> +static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
> >> +{
> >> + assert(srcno < xsrc->nr_irqs);
> >> + return xsrc->status[srcno] & XIVE_STATUS_LSI;
> >> +}
> >> +
> >> +static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
> >> + bool lsi)
> >> +{
> >> + assert(srcno < xsrc->nr_irqs);
> >> + xsrc->status[srcno] |= lsi ? XIVE_STATUS_LSI : 0;
> >> +}
> >> +
> >> #endif /* PPC_XIVE_H */
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2018-04-24 7:48 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-19 12:42 [Qemu-devel] [PATCH v3 00/35] ppc: support for the XIVE interrupt controller (POWER9) Cédric Le Goater
2018-04-19 12:42 ` [Qemu-devel] [PATCH v3 01/35] ppc/xive: introduce a XIVE interrupt source model Cédric Le Goater
2018-04-20 7:10 ` David Gibson
2018-04-20 8:27 ` Cédric Le Goater
2018-04-23 3:59 ` David Gibson
2018-04-23 7:11 ` Cédric Le Goater
2018-04-24 1:24 ` David Gibson
2018-04-19 12:42 ` [Qemu-devel] [PATCH v3 02/35] ppc/xive: add support for the LSI interrupt sources Cédric Le Goater
2018-04-23 6:44 ` David Gibson
2018-04-23 7:31 ` Cédric Le Goater
2018-04-24 6:41 ` David Gibson [this message]
2018-04-24 8:11 ` Cédric Le Goater
2018-04-26 3:28 ` David Gibson
2018-04-26 12:16 ` Cédric Le Goater
2018-04-27 2:43 ` David Gibson
2018-05-04 14:25 ` Cédric Le Goater
2018-05-05 4:32 ` David Gibson
2018-04-19 12:42 ` [Qemu-devel] [PATCH v3 03/35] ppc/xive: introduce the XiveFabric interface Cédric Le Goater
2018-04-23 6:46 ` David Gibson
2018-04-23 7:58 ` Cédric Le Goater
2018-04-24 6:46 ` David Gibson
2018-04-24 9:33 ` Cédric Le Goater
2018-04-26 3:54 ` David Gibson
2018-04-26 10:30 ` Cédric Le Goater
2018-04-27 6:32 ` David Gibson
2018-05-02 15:28 ` Cédric Le Goater
2018-05-03 5:13 ` David Gibson
2018-05-23 10:12 ` Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 04/35] spapr/xive: introduce a XIVE interrupt controller for sPAPR Cédric Le Goater
2018-04-24 6:51 ` David Gibson
2018-04-24 9:46 ` Cédric Le Goater
2018-04-26 4:20 ` David Gibson
2018-04-26 10:43 ` Cédric Le Goater
2018-05-03 5:22 ` David Gibson
2018-05-03 16:50 ` Cédric Le Goater
2018-05-04 3:33 ` David Gibson
2018-05-04 13:05 ` Cédric Le Goater
2018-05-05 4:26 ` David Gibson
2018-05-09 7:23 ` Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 05/35] spapr/xive: add a single source block to the sPAPR XIVE model Cédric Le Goater
2018-04-24 6:58 ` David Gibson
2018-04-24 8:19 ` Cédric Le Goater
2018-04-26 4:46 ` David Gibson
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 06/35] spapr/xive: introduce a XIVE interrupt presenter model Cédric Le Goater
2018-04-26 7:11 ` David Gibson
2018-04-26 9:27 ` Cédric Le Goater
2018-04-26 17:15 ` Cédric Le Goater
2018-05-03 5:39 ` David Gibson
2018-05-03 15:10 ` Cédric Le Goater
2018-05-04 4:44 ` David Gibson
2018-05-04 14:15 ` Cédric Le Goater
2018-05-03 5:35 ` David Gibson
2018-05-03 16:06 ` Cédric Le Goater
2018-05-04 4:51 ` David Gibson
2018-05-04 13:11 ` Cédric Le Goater
2018-05-05 4:27 ` David Gibson
2018-05-09 7:27 ` Cédric Le Goater
2018-05-02 7:39 ` Cédric Le Goater
2018-05-03 5:43 ` David Gibson
2018-05-03 14:42 ` Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 07/35] spapr/xive: introduce the XIVE Event Queues Cédric Le Goater
2018-04-26 7:25 ` David Gibson
2018-04-26 9:48 ` Cédric Le Goater
2018-05-03 5:45 ` David Gibson
2018-05-03 6:07 ` Cédric Le Goater
2018-05-03 6:25 ` David Gibson
2018-05-03 14:37 ` Cédric Le Goater
2018-05-04 5:19 ` David Gibson
2018-05-04 13:29 ` Cédric Le Goater
2018-05-05 4:29 ` David Gibson
2018-05-09 8:01 ` Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 08/35] spapr: push the XIVE EQ data in OS event queue Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 09/35] spapr: notify the CPU when the XIVE interrupt priority is more privileged Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 10/35] spapr: add support for the SET_OS_PENDING command (XIVE) Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 11/35] spapr: introduce a 'xive_exploitation' option to enable XIVE Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 12/35] spapr: add a sPAPRXive object to the machine Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 13/35] spapr: add hcalls support for the XIVE exploitation interrupt mode Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 14/35] spapr: add device tree support for the XIVE exploitation mode Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 15/35] sysbus: add a sysbus_mmio_unmap() helper Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 16/35] spapr: introduce a helper to map the XIVE memory regions Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 17/35] spapr: add XIVE support to spapr_qirq() Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 18/35] spapr: introduce a spapr_icp_create() helper Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 19/35] spapr: toggle the ICP depending on the selected interrupt mode Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 20/35] spapr: add support to dump XIVE information Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 21/35] spapr: advertise XIVE exploitation mode in CAS Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 22/35] spapr: add classes for the XIVE models Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 23/35] target/ppc/kvm: add Linux KVM definitions for XIVE Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 24/35] spapr/xive: add common realize routine for KVM Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 25/35] spapr/xive: add KVM support Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 26/35] spapr/xive: add a XIVE KVM device to the machine Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 27/35] migration: discard non-migratable RAMBlocks Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 28/35] intc: introduce a CPUIntc interface Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 29/35] spapr/xive, xics: use the CPU_INTC handlers to reset KVM Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 30/35] spapr/xive, xics: reset KVM at machine reset Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 31/35] spapr/xive: raise migration priority of the machine Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 32/35] ppc/pnv: introduce a pnv_icp_create() helper Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 33/35] ppc: externalize ppc_get_vcpu_by_pir() Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 34/35] ppc/pnv: add XIVE support Cédric Le Goater
2018-04-19 12:43 ` [Qemu-devel] [PATCH v3 35/35] ppc/pnv: add a PSI bridge model for POWER9 processor Cédric Le Goater
2018-04-19 13:28 ` [Qemu-devel] [PATCH v3 00/35] ppc: support for the XIVE interrupt controller (POWER9) no-reply
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