From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fB99Q-0003zI-GP for qemu-devel@nongnu.org; Tue, 24 Apr 2018 21:23:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fB99P-0007MA-Km for qemu-devel@nongnu.org; Tue, 24 Apr 2018 21:23:16 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:35737) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fB99P-0007KO-Ek for qemu-devel@nongnu.org; Tue, 24 Apr 2018 21:23:15 -0400 Received: by mail-pf0-x241.google.com with SMTP id j5so13752383pfh.2 for ; Tue, 24 Apr 2018 18:23:15 -0700 (PDT) From: Richard Henderson Date: Tue, 24 Apr 2018 15:22:55 -1000 Message-Id: <20180425012300.14698-5-richard.henderson@linaro.org> In-Reply-To: <20180425012300.14698-1-richard.henderson@linaro.org> References: <20180425012300.14698-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 4/9] target/arm: Clear SVE high bits for FMOV List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Use write_fp_dreg and clear_vec_high to zero the bits that need zeroing for these cases. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b27892d971..f2241d8174 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5356,31 +5356,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) if (itof) { TCGv_i64 tcg_rn = cpu_reg(s, rn); + TCGv_i64 tmp; switch (type) { case 0: - { /* 32 bit */ - TCGv_i64 tmp = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, tcg_rn); - tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64)); - tcg_gen_movi_i64(tmp, 0); - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); + write_fp_dreg(s, rd, tmp); tcg_temp_free_i64(tmp); break; - } case 1: - { /* 64 bit */ - TCGv_i64 tmp = tcg_const_i64(0); - tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64)); - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); - tcg_temp_free_i64(tmp); + write_fp_dreg(s, rd, tcg_rn); break; - } case 2: /* 64 bit to top half. */ tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); + clear_vec_high(s, true, rd); break; } } else { -- 2.14.3