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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 06/19] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
Date: Thu, 26 Apr 2018 11:47:02 +0100	[thread overview]
Message-ID: <20180426104715.21702-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180426104715.21702-1-peter.maydell@linaro.org>

From: Aaron Lindsay <alindsay@codeaurora.org>

They share the same underlying state

Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1523997485-1905-3-git-send-email-alindsay@codeaurora.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1526724d64..7bf4afa719 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1318,7 +1318,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
       .writefn = pmselr_write, .raw_writefn = raw_write, },
     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
-      .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
+      .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
       .readfn = pmccntr_read, .writefn = pmccntr_write32,
       .accessfn = pmreg_access_ccntr },
     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
-- 
2.17.0

  parent reply	other threads:[~2018-04-26 10:47 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-26 10:46 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2018-04-26 10:46 ` [Qemu-devel] [PULL 01/19] device_tree: Increase FDT_MAX_SIZE to 1 MiB Peter Maydell
2018-04-26 10:46 ` [Qemu-devel] [PULL 02/19] arm: always start from first_cpu when registering loader cpu reset callback Peter Maydell
2018-04-26 10:46 ` [Qemu-devel] [PULL 03/19] target/arm: Remove stale TODO comment Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 04/19] target/arm: Use v7m_stack_read() for reading the frame signature Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 05/19] target/arm: Check PMCNTEN for whether PMCCNTR is enabled Peter Maydell
2018-04-26 10:47 ` Peter Maydell [this message]
2018-04-26 10:47 ` [Qemu-devel] [PULL 07/19] target/arm: Mask PMU register writes based on PMCR_EL0.N Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 08/19] target/arm: Fetch GICv3 state directly from CPUARMState Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 09/19] target/arm: Support multiple EL change hooks Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 10/19] target/arm: Add pre-EL " Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 11/19] target/arm: Allow EL change hooks to do IO Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 12/19] target/arm: Fix bitmask for PMCCFILTR writes Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 13/19] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 14/19] hw/arm/raspi: Don't bother setting default_cpu_type Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 15/19] hw/arm/highbank: don't make sysram 'nomigrate' Peter Maydell
2018-04-26 22:03   ` Michael Clark
2018-04-27 10:10     ` Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 16/19] hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate' Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 17/19] hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 18/19] timer/aspeed: fix vmstate version id Peter Maydell
2018-04-26 10:47 ` [Qemu-devel] [PULL 19/19] xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo Peter Maydell
2018-04-26 12:15 ` [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell

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