[Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30

[Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

The following changes since commit 6f0c4706b35dead265509115ddbd2a8d1af516c1:

  Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180427-pull-request' into staging (2018-04-27 12:27:59 +0100)

are available in the git repository at:

  git@github.com:edgarigl/qemu.git tags/edgar/xilinx-next-2018-04-30.for-upstream

for you to fetch changes up to fce6a8eceb07e27f0cdea87427f4e560dfa0b1c8:

  target-microblaze: mmu: Make the TLBX MISS bit read-only (2018-04-30 16:43:20 +0200)

----------------------------------------------------------------
edgar/xilinx-next-2018-01.for-upstream

----------------------------------------------------------------
Edgar E. Iglesias (5):
      target-microblaze: Respect MSR.PVR as read-only
      target-microblaze: Fix trap checks for FPU insns
      target-microblaze: Don't clobber the IMM reg for ld/st reversed
      target-microblaze: mmu: Make TLBSX write-only
      target-microblaze: mmu: Make the TLBX MISS bit read-only

 target/microblaze/mmu.c       | 9 ++++++++-
 target/microblaze/translate.c | 6 ++----
 2 files changed, 10 insertions(+), 5 deletions(-)

Edgar E. Iglesias (5):
  target-microblaze: Respect MSR.PVR as read-only
  target-microblaze: Fix trap checks for FPU insns
  target-microblaze: Don't clobber the IMM reg for ld/st reversed
  target-microblaze: mmu: Make TLBSX write-only
  target-microblaze: mmu: Make the TLBX MISS bit read-only

 target/microblaze/mmu.c       | 9 ++++++++-
 target/microblaze/translate.c | 6 ++----
 2 files changed, 10 insertions(+), 5 deletions(-)

-- 
2.14.1

[Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 7628b0e25b..f739751930 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -424,7 +424,7 @@ static inline void msr_write(DisasContext *dc, TCGv v)
     /* PVR bit is not writable.  */
     tcg_gen_andi_tl(t, v, ~MSR_PVR);
     tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
-    tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
+    tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t);
     tcg_temp_free(t);
 }
 
-- 
2.14.1

[Qemu-devel] [PULL v1 2/5] target-microblaze: Fix trap checks for FPU insns

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix trap checks for FPU insns when extended FPU insns are enabled.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index f739751930..ec12fed49d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-          && (dc->cpu->cfg.use_fpu != 1)) {
+          && !dc->cpu->cfg.use_fpu) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
         return;
-- 
2.14.1

[Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Do not clobber the IMM register on reversed load/stores.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ec12fed49d..100883e2cc 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -952,7 +952,6 @@ static void dec_load(DisasContext *dc)
                 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
                 tcg_gen_andi_tl(t, t, ~3);
                 tcg_gen_or_tl(t, t, low);
-                tcg_gen_mov_tl(env_imm, t);
                 tcg_temp_free(low);
                 break;
             }
@@ -1104,7 +1103,6 @@ static void dec_store(DisasContext *dc)
                 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
                 tcg_gen_andi_tl(t, t, ~3);
                 tcg_gen_or_tl(t, t, low);
-                tcg_gen_mov_tl(env_imm, t);
                 tcg_temp_free(low);
                 break;
             }
-- 
2.14.1

[Qemu-devel] [PULL v1 4/5] target-microblaze: mmu: Make TLBSX write-only

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Make TLBSX write-only and guest-error log reads from it.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/mmu.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index a0f06758f8..8391811900 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -182,7 +182,7 @@ done:
 uint32_t mmu_read(CPUMBState *env, uint32_t rn)
 {
     unsigned int i;
-    uint32_t r;
+    uint32_t r = 0;
 
     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
         qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
@@ -211,6 +211,9 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
             }
             r = env->mmu.regs[rn];
             break;
+        case MMU_R_TLBSX:
+            qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");
+            break;
         default:
             r = env->mmu.regs[rn];
             break;
-- 
2.14.1

[Qemu-devel] [PULL v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Make the TLBX MISS bit read-only.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/mmu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 8391811900..9d5e6aa8a5 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -273,6 +273,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
                 env->mmu.regs[rn] = v;
             }
             break;
+        case MMU_R_TLBX:
+            /* Bit 31 is read-only.  */
+            env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
+            break;
         case MMU_R_TLBSX:
         {
             struct microblaze_mmu_lookup lu;
-- 
2.14.1

Re: [Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30

[Peter Maydell]

On 30 April 2018 at 16:08, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> The following changes since commit 6f0c4706b35dead265509115ddbd2a8d1af516c1:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180427-pull-request' into staging (2018-04-27 12:27:59 +0100)
>
> are available in the git repository at:
>
>   git@github.com:edgarigl/qemu.git tags/edgar/xilinx-next-2018-04-30.for-upstream
>
> for you to fetch changes up to fce6a8eceb07e27f0cdea87427f4e560dfa0b1c8:
>
>   target-microblaze: mmu: Make the TLBX MISS bit read-only (2018-04-30 16:43:20 +0200)
>
> ----------------------------------------------------------------
> edgar/xilinx-next-2018-01.for-upstream
>
> ----------------------------------------------------------------
> Edgar E. Iglesias (5):
>       target-microblaze: Respect MSR.PVR as read-only
>       target-microblaze: Fix trap checks for FPU insns
>       target-microblaze: Don't clobber the IMM reg for ld/st reversed
>       target-microblaze: mmu: Make TLBSX write-only
>       target-microblaze: mmu: Make the TLBX MISS bit read-only
>
>  target/microblaze/mmu.c       | 9 ++++++++-
>  target/microblaze/translate.c | 6 ++----
>  2 files changed, 10 insertions(+), 5 deletions(-)
>
> Edgar E. Iglesias (5):
>   target-microblaze: Respect MSR.PVR as read-only
>   target-microblaze: Fix trap checks for FPU insns
>   target-microblaze: Don't clobber the IMM reg for ld/st reversed
>   target-microblaze: mmu: Make TLBSX write-only
>   target-microblaze: mmu: Make the TLBX MISS bit read-only
>
>  target/microblaze/mmu.c       | 9 ++++++++-
>  target/microblaze/translate.c | 6 ++----
>  2 files changed, 10 insertions(+), 5 deletions(-)

Applied, thanks.

-- PMM