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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PATCH 09/13] target/openrisc: Convert dec_M
Date: Thu,  3 May 2018 22:40:26 -0700	[thread overview]
Message-ID: <20180504054030.24527-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180504054030.24527-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/translate.c  | 41 +++++++++++++----------------------------
 target/openrisc/insns.decode |  3 +++
 2 files changed, 16 insertions(+), 28 deletions(-)

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index f2f9a0c0d2..548e0230b3 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1031,32 +1031,21 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
     return true;
 }
 
-static void dec_M(DisasContext *dc, uint32_t insn)
+static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn)
 {
-    uint32_t op0;
-    uint32_t rd;
-    uint32_t K16;
-    op0 = extract32(insn, 16, 1);
-    rd = extract32(insn, 21, 5);
-    K16 = extract32(insn, 0, 16);
+    LOG_DIS("l.movhi r%d, %d\n", a->d, a->k);
+    check_r0_write(a->d);
+    tcg_gen_movi_tl(cpu_R[a->d], a->k << 16);
+    return true;
+}
 
-    check_r0_write(rd);
-    switch (op0) {
-    case 0x0:    /* l.movhi */
-        LOG_DIS("l.movhi  r%d, %d\n", rd, K16);
-        tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
-        break;
-
-    case 0x1:    /* l.macrc */
-        LOG_DIS("l.macrc  r%d\n", rd);
-        tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac);
-        tcg_gen_movi_i64(cpu_mac, 0);
-        break;
-
-    default:
-        gen_illegal_exception(dc);
-        break;
-    }
+static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
+{
+    LOG_DIS("l.macrc r%d\n", a->d);
+    check_r0_write(a->d);
+    tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac);
+    tcg_gen_movi_i64(cpu_mac, 0);
+    return true;
 }
 
 static void dec_comp(DisasContext *dc, uint32_t insn)
@@ -1481,10 +1470,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
 
     op0 = extract32(insn, 26, 6);
     switch (op0) {
-    case 0x06:
-        dec_M(dc, insn);
-        break;
-
     case 0x2f:
         dec_compi(dc, insn);
         break;
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index fb8ba5812a..84f71c13b3 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -95,6 +95,9 @@ l_mtspr         110000 ..... a:5 b:5 ...........        k=%mtspr_k
 
 l_maci          010011 ----- a:5 i:s16
 
+l_movhi         000110 d:5 ----0 k:16
+l_macrc         000110 d:5 ----1 00000000 00000000
+
 ####
 # Arithmetic Instructions
 ####
-- 
2.14.3

  parent reply	other threads:[~2018-05-04  5:40 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-04  5:40 [Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py Richard Henderson
2018-05-04  5:40 ` [Qemu-devel] [PATCH 01/13] target-openrisc: Write back result before FPE exception Richard Henderson
2018-05-05  5:19   ` Stafford Horne
2018-05-05 11:08     ` BAndViG
2018-05-04  5:40 ` [Qemu-devel] [PATCH 02/13] target/openrisc: Start conversion to decodetree.py Richard Henderson
2018-05-05  5:22   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 03/13] target/openrisc: Convert branch insns Richard Henderson
2018-05-05  5:25   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 04/13] target/openrisc: Convert memory insns Richard Henderson
2018-05-05  5:27   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 05/13] target/openrisc: Convert remainder of dec_misc insns Richard Henderson
2018-05-05  5:32   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 06/13] target/openrisc: Convert dec_calc Richard Henderson
2018-05-05  5:34   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 07/13] target/openrisc: Convert dec_mac Richard Henderson
2018-05-05  5:35   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 08/13] target/openrisc: Convert dec_logic Richard Henderson
2018-05-05  5:37   ` Stafford Horne
2018-05-04  5:40 ` Richard Henderson [this message]
2018-05-05  5:39   ` [Qemu-devel] [PATCH 09/13] target/openrisc: Convert dec_M Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 10/13] target/openrisc: Convert dec_comp Richard Henderson
2018-05-05  5:39   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 11/13] target/openrisc: Convert dec_compi Richard Henderson
2018-05-05  5:41   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 12/13] target/openrisc: Convert dec_float Richard Henderson
2018-05-05  5:45   ` Stafford Horne
2018-05-04  5:40 ` [Qemu-devel] [PATCH 13/13] target/openrisc: Merge disas_openrisc_insn Richard Henderson
2018-05-05  5:46   ` Stafford Horne
2018-05-05  5:49 ` [Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py Stafford Horne
2018-05-05 15:15   ` Richard Henderson

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