From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PATCH 13/13] target/openrisc: Merge disas_openrisc_insn
Date: Thu, 3 May 2018 22:40:30 -0700 [thread overview]
Message-ID: <20180504054030.24527-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180504054030.24527-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 66e493220e..3866106bf6 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1373,14 +1373,6 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn)
return true;
}
-static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
-{
- uint32_t insn = cpu_ldl_code(&cpu->env, dc->pc);
- if (!decode(dc, insn)) {
- gen_illegal_exception(dc);
- }
-}
-
void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
CPUOpenRISCState *env = cs->env_ptr;
@@ -1388,6 +1380,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;
+ uint32_t insn;
int num_insns;
int max_insns;
@@ -1449,7 +1442,11 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
- disas_openrisc_insn(dc, cpu);
+
+ insn = cpu_ldl_code(&cpu->env, dc->pc);
+ if (!decode(dc, insn)) {
+ gen_illegal_exception(dc);
+ }
dc->pc = dc->pc + 4;
/* delay slot */
--
2.14.3
next prev parent reply other threads:[~2018-05-04 5:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-04 5:40 [Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py Richard Henderson
2018-05-04 5:40 ` [Qemu-devel] [PATCH 01/13] target-openrisc: Write back result before FPE exception Richard Henderson
2018-05-05 5:19 ` Stafford Horne
2018-05-05 11:08 ` BAndViG
2018-05-04 5:40 ` [Qemu-devel] [PATCH 02/13] target/openrisc: Start conversion to decodetree.py Richard Henderson
2018-05-05 5:22 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 03/13] target/openrisc: Convert branch insns Richard Henderson
2018-05-05 5:25 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 04/13] target/openrisc: Convert memory insns Richard Henderson
2018-05-05 5:27 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 05/13] target/openrisc: Convert remainder of dec_misc insns Richard Henderson
2018-05-05 5:32 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 06/13] target/openrisc: Convert dec_calc Richard Henderson
2018-05-05 5:34 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 07/13] target/openrisc: Convert dec_mac Richard Henderson
2018-05-05 5:35 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 08/13] target/openrisc: Convert dec_logic Richard Henderson
2018-05-05 5:37 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 09/13] target/openrisc: Convert dec_M Richard Henderson
2018-05-05 5:39 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 10/13] target/openrisc: Convert dec_comp Richard Henderson
2018-05-05 5:39 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 11/13] target/openrisc: Convert dec_compi Richard Henderson
2018-05-05 5:41 ` Stafford Horne
2018-05-04 5:40 ` [Qemu-devel] [PATCH 12/13] target/openrisc: Convert dec_float Richard Henderson
2018-05-05 5:45 ` Stafford Horne
2018-05-04 5:40 ` Richard Henderson [this message]
2018-05-05 5:46 ` [Qemu-devel] [PATCH 13/13] target/openrisc: Merge disas_openrisc_insn Stafford Horne
2018-05-05 5:49 ` [Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py Stafford Horne
2018-05-05 15:15 ` Richard Henderson
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