* [Qemu-devel] [PULL 00/24] target-arm queue
@ 2018-05-04 17:55 Peter Maydell
2018-05-08 9:50 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2018-05-04 17:55 UTC (permalink / raw)
To: qemu-devel
v2: fixed format string errors in trace messages.
-- PMM
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180504-1
for you to fetch changes up to e24e3454829579eb815ec95d7b3679b0f65845b4:
hw/arm/virt: Introduce the iommu option (2018-05-04 18:52:58 +0100)
----------------------------------------------------------------
target-arm queue:
* Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board
if the commandline includes "-machine iommu=smmuv3"
* target/arm: Implement v8M VLLDM and VLSTM
* hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
* Some fixes to silence Coverity false-positives
* arm: boot: set boot_info starting from first_cpu
(fixes a technical bug not visible in practice)
* hw/net/smc91c111: Convert away from old_mmio
* hw/usb/tusb6010: Convert away from old_mmio
* hw/char/cmsdk-apb-uart.c: Accept more input after character read
* target/arm: Make MPUIR write-ignored on OMAP, StrongARM
* hw/arm/virt: Add linux,pci-domain property
----------------------------------------------------------------
Eric Auger (11):
hw/arm/smmu-common: smmu base device and datatypes
hw/arm/smmu-common: IOMMU memory region and address space setup
hw/arm/smmu-common: VMSAv8-64 page table walk
hw/arm/smmuv3: Wired IRQ and GERROR helpers
hw/arm/smmuv3: Queue helpers
hw/arm/smmuv3: Implement MMIO write operations
hw/arm/smmuv3: Event queue recording helper
hw/arm/smmuv3: Implement translate callback
hw/arm/smmuv3: Abort on vfio or vhost case
target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
hw/arm/virt: Introduce the iommu option
Igor Mammedov (1):
arm: boot: set boot_info starting from first_cpu
Jan Kiszka (1):
hw/arm/virt: Add linux,pci-domain property
Mathew Maidment (1):
target/arm: Correct MPUIR privilege level in register_cp_regs_for_features() conditional case
Patrick Oppenlander (1):
hw/char/cmsdk-apb-uart.c: Accept more input after character read
Peter Maydell (3):
hw/usb/tusb6010: Convert away from old_mmio
hw/net/smc91c111: Convert away from old_mmio
target/arm: Implement v8M VLLDM and VLSTM
Prem Mallappa (3):
hw/arm/smmuv3: Skeleton
hw/arm/virt: Add SMMUv3 to the virt board
hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
Richard Henderson (2):
target/arm: Tidy conditions in handle_vec_simd_shri
target/arm: Tidy condition in disas_simd_two_reg_misc
Thomas Huth (1):
hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
hw/arm/Makefile.objs | 1 +
hw/arm/smmu-internal.h | 99 +++
hw/arm/smmuv3-internal.h | 621 ++++++++++++++++++
include/hw/acpi/acpi-defs.h | 15 +
include/hw/arm/smmu-common.h | 145 +++++
include/hw/arm/smmuv3.h | 87 +++
include/hw/arm/virt.h | 10 +
hw/arm/boot.c | 2 +-
hw/arm/omap1.c | 8 +-
hw/arm/omap2.c | 8 +-
hw/arm/pxa2xx.c | 15 +-
hw/arm/smmu-common.c | 372 +++++++++++
hw/arm/smmuv3.c | 1191 +++++++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 55 +-
hw/arm/virt.c | 101 ++-
hw/char/cmsdk-apb-uart.c | 1 +
hw/net/smc91c111.c | 54 +-
hw/usb/tusb6010.c | 40 +-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 38 +-
target/arm/translate-a64.c | 12 +-
target/arm/translate.c | 17 +-
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/trace-events | 37 ++
target/arm/trace-events | 3 +
25 files changed, 2868 insertions(+), 67 deletions(-)
create mode 100644 hw/arm/smmu-internal.h
create mode 100644 hw/arm/smmuv3-internal.h
create mode 100644 include/hw/arm/smmu-common.h
create mode 100644 include/hw/arm/smmuv3.h
create mode 100644 hw/arm/smmu-common.c
create mode 100644 hw/arm/smmuv3.c
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2018-05-04 17:55 [Qemu-devel] [PULL 00/24] target-arm queue Peter Maydell
@ 2018-05-08 9:50 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2018-05-08 9:50 UTC (permalink / raw)
To: QEMU Developers
On 4 May 2018 at 18:55, Peter Maydell <peter.maydell@linaro.org> wrote:
> v2: fixed format string errors in trace messages.
>
> -- PMM
>
> The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:
>
> Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180504-1
>
> for you to fetch changes up to e24e3454829579eb815ec95d7b3679b0f65845b4:
>
> hw/arm/virt: Introduce the iommu option (2018-05-04 18:52:58 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board
> if the commandline includes "-machine iommu=smmuv3"
> * target/arm: Implement v8M VLLDM and VLSTM
> * hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
> * Some fixes to silence Coverity false-positives
> * arm: boot: set boot_info starting from first_cpu
> (fixes a technical bug not visible in practice)
> * hw/net/smc91c111: Convert away from old_mmio
> * hw/usb/tusb6010: Convert away from old_mmio
> * hw/char/cmsdk-apb-uart.c: Accept more input after character read
> * target/arm: Make MPUIR write-ignored on OMAP, StrongARM
> * hw/arm/virt: Add linux,pci-domain property
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/24] target-arm queue
@ 2019-06-17 14:33 Peter Maydell
2019-06-17 15:41 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2019-06-17 14:33 UTC (permalink / raw)
To: qemu-devel
Latest arm queue, half minor code cleanups and half minor
bug fixes.
-- PMM
The following changes since commit 5d0e5694470d2952b4f257bc985cac8c89b4fd92:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-06-17 11:55:14 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190617
for you to fetch changes up to 1120827fa182f0e76226df7ffe7a86598d1df54f:
target/arm: Only implement doubles if the FPU supports them (2019-06-17 15:15:06 +0100)
----------------------------------------------------------------
target-arm queue:
* support large kernel images in bootloader (by avoiding
putting the initrd over the top of them)
* correctly disable FPU/DSP in the CPU for the mps2-an521, musca-a boards
* arm_gicv3: Fix decoding of ID register range
* arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
* some code cleanups following on from the VFP decodetree conversion
* Only implement doubles if the FPU supports them
(so we now correctly model Cortex-M4, -M33 as single precision only)
----------------------------------------------------------------
Peter Maydell (24):
hw/arm/boot: Don't assume RAM starts at address zero
hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM
hw/arm/boot: Avoid placing the initrd on top of the kernel
hw/arm/boot: Honour image size field in AArch64 Image format kernels
target/arm: Allow VFP and Neon to be disabled via a CPU property
target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property
hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU
hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards
hw/intc/arm_gicv3: Fix decoding of ID register range
hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
target/arm: Move vfp_expand_imm() to translate.[ch]
target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm
target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F
target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F
target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*
target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]
target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F
target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT
target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops
target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32
target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16
target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d
target/arm: Fix typos in trans function prototypes
target/arm: Only implement doubles if the FPU supports them
include/hw/arm/armsse.h | 7 ++
include/hw/arm/armv7m.h | 4 +
target/arm/cpu.h | 12 +++
target/arm/translate-a64.h | 1 -
target/arm/translate.h | 7 ++
hw/arm/armsse.c | 58 +++++++---
hw/arm/armv7m.c | 18 ++++
hw/arm/boot.c | 83 ++++++++++----
hw/arm/musca.c | 8 ++
hw/intc/arm_gicv3_dist.c | 12 ++-
hw/intc/arm_gicv3_redist.c | 4 +-
target/arm/cpu.c | 179 ++++++++++++++++++++++++++++--
target/arm/translate-a64.c | 32 ------
target/arm/translate-vfp.inc.c | 173 ++++++++++++++++++++++-------
target/arm/translate.c | 240 ++++++++++++++---------------------------
target/arm/vfp.decode | 10 +-
16 files changed, 572 insertions(+), 276 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2019-06-17 14:33 Peter Maydell
@ 2019-06-17 15:41 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2019-06-17 15:41 UTC (permalink / raw)
To: QEMU Developers
On Mon, 17 Jun 2019 at 15:34, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Latest arm queue, half minor code cleanups and half minor
> bug fixes.
>
> -- PMM
>
> The following changes since commit 5d0e5694470d2952b4f257bc985cac8c89b4fd92:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-06-17 11:55:14 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190617
>
> for you to fetch changes up to 1120827fa182f0e76226df7ffe7a86598d1df54f:
>
> target/arm: Only implement doubles if the FPU supports them (2019-06-17 15:15:06 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * support large kernel images in bootloader (by avoiding
> putting the initrd over the top of them)
> * correctly disable FPU/DSP in the CPU for the mps2-an521, musca-a boards
> * arm_gicv3: Fix decoding of ID register range
> * arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
> * some code cleanups following on from the VFP decodetree conversion
> * Only implement doubles if the FPU supports them
> (so we now correctly model Cortex-M4, -M33 as single precision only)
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/24] target-arm queue
@ 2018-05-04 17:15 Peter Maydell
2018-05-04 17:58 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2018-05-04 17:15 UTC (permalink / raw)
To: qemu-devel
target-arm queue: Eric's SMMUv3 patchset, and an array
of minor bugfixes and improvements from various others.
thanks
-- PMM
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180504
for you to fetch changes up to 5680740c92993e9b3f3e011f2a2c394070e33f56:
hw/arm/virt: Introduce the iommu option (2018-05-04 18:05:52 +0100)
----------------------------------------------------------------
target-arm queue:
* Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board
if the commandline includes "-machine iommu=smmuv3"
* target/arm: Implement v8M VLLDM and VLSTM
* hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
* Some fixes to silence Coverity false-positives
* arm: boot: set boot_info starting from first_cpu
(fixes a technical bug not visible in practice)
* hw/net/smc91c111: Convert away from old_mmio
* hw/usb/tusb6010: Convert away from old_mmio
* hw/char/cmsdk-apb-uart.c: Accept more input after character read
* target/arm: Make MPUIR write-ignored on OMAP, StrongARM
* hw/arm/virt: Add linux,pci-domain property
----------------------------------------------------------------
Eric Auger (11):
hw/arm/smmu-common: smmu base device and datatypes
hw/arm/smmu-common: IOMMU memory region and address space setup
hw/arm/smmu-common: VMSAv8-64 page table walk
hw/arm/smmuv3: Wired IRQ and GERROR helpers
hw/arm/smmuv3: Queue helpers
hw/arm/smmuv3: Implement MMIO write operations
hw/arm/smmuv3: Event queue recording helper
hw/arm/smmuv3: Implement translate callback
hw/arm/smmuv3: Abort on vfio or vhost case
target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
hw/arm/virt: Introduce the iommu option
Igor Mammedov (1):
arm: boot: set boot_info starting from first_cpu
Jan Kiszka (1):
hw/arm/virt: Add linux,pci-domain property
Mathew Maidment (1):
target/arm: Correct MPUIR privilege level in register_cp_regs_for_features() conditional case
Patrick Oppenlander (1):
hw/char/cmsdk-apb-uart.c: Accept more input after character read
Peter Maydell (3):
hw/usb/tusb6010: Convert away from old_mmio
hw/net/smc91c111: Convert away from old_mmio
target/arm: Implement v8M VLLDM and VLSTM
Prem Mallappa (3):
hw/arm/smmuv3: Skeleton
hw/arm/virt: Add SMMUv3 to the virt board
hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
Richard Henderson (2):
target/arm: Tidy conditions in handle_vec_simd_shri
target/arm: Tidy condition in disas_simd_two_reg_misc
Thomas Huth (1):
hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
hw/arm/Makefile.objs | 1 +
hw/arm/smmu-internal.h | 99 +++
hw/arm/smmuv3-internal.h | 621 ++++++++++++++++++
include/hw/acpi/acpi-defs.h | 15 +
include/hw/arm/smmu-common.h | 145 +++++
include/hw/arm/smmuv3.h | 87 +++
include/hw/arm/virt.h | 10 +
hw/arm/boot.c | 2 +-
hw/arm/omap1.c | 8 +-
hw/arm/omap2.c | 8 +-
hw/arm/pxa2xx.c | 15 +-
hw/arm/smmu-common.c | 372 +++++++++++
hw/arm/smmuv3.c | 1191 +++++++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 55 +-
hw/arm/virt.c | 101 ++-
hw/char/cmsdk-apb-uart.c | 1 +
hw/net/smc91c111.c | 54 +-
hw/usb/tusb6010.c | 40 +-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 38 +-
target/arm/translate-a64.c | 12 +-
target/arm/translate.c | 17 +-
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/trace-events | 37 ++
target/arm/trace-events | 3 +
25 files changed, 2868 insertions(+), 67 deletions(-)
create mode 100644 hw/arm/smmu-internal.h
create mode 100644 hw/arm/smmuv3-internal.h
create mode 100644 include/hw/arm/smmu-common.h
create mode 100644 include/hw/arm/smmuv3.h
create mode 100644 hw/arm/smmu-common.c
create mode 100644 hw/arm/smmuv3.c
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2018-05-04 17:15 Peter Maydell
@ 2018-05-04 17:58 ` Peter Maydell
2018-05-06 16:00 ` Auger Eric
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2018-05-04 17:58 UTC (permalink / raw)
To: QEMU Developers, Eric Auger
On 4 May 2018 at 18:15, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm queue: Eric's SMMUv3 patchset, and an array
> of minor bugfixes and improvements from various others.
>
> thanks
> -- PMM
>
> The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:
>
> Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180504
>
> for you to fetch changes up to 5680740c92993e9b3f3e011f2a2c394070e33f56:
>
> hw/arm/virt: Introduce the iommu option (2018-05-04 18:05:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board
> if the commandline includes "-machine iommu=smmuv3"
> * target/arm: Implement v8M VLLDM and VLSTM
> * hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
> * Some fixes to silence Coverity false-positives
> * arm: boot: set boot_info starting from first_cpu
> (fixes a technical bug not visible in practice)
> * hw/net/smc91c111: Convert away from old_mmio
> * hw/usb/tusb6010: Convert away from old_mmio
> * hw/char/cmsdk-apb-uart.c: Accept more input after character read
> * target/arm: Make MPUIR write-ignored on OMAP, StrongARM
> * hw/arm/virt: Add linux,pci-domain property
Oops, 32-bit compile failures for format string issues;
hw/arm/trace.h: In function ‘_nocheck__trace_smmu_ptw_level’:
hw/arm/trace.h:215:18: error: format ‘%lx’ expects argument of type
‘long unsigned int’, but argument 7 has type ‘size_t {aka unsigned
int}’ [-Werror=format=]
qemu_log("%d@%zd.%06zd:smmu_ptw_level " "level=%d
iova=0x%"PRIx64" subpage_sz=0x%lx baseaddr=0x%"PRIx64" offset=%d =>
pte=0x%"PRIx64 "\n",
^
hw/arm/trace.h: In function ‘_nocheck__trace_smmuv3_write_mmio_idr’:
hw/arm/trace.h:606:18: error: format ‘%lx’ expects argument of type
‘long unsigned int’, but argument 5 has type ‘uint64_t {aka long long
unsigned int}’ [-Werror=format=]
qemu_log("%d@%zd.%06zd:smmuv3_write_mmio_idr " "write to
RO/Unimpl reg 0x%lx val64:0x%lx" "\n",
^
hw/arm/trace.h:606:18: error: format ‘%lx’ expects argument of type
‘long unsigned int’, but argument 6 has type ‘uint64_t {aka long long
unsigned int}’ [-Werror=format=]
hw/arm/trace.h: In function ‘_nocheck__trace_smmuv3_find_ste_2lvl’:
hw/arm/trace.h:721:18: error: format ‘%lx’ expects argument of type
‘long unsigned int’, but argument 5 has type ‘uint64_t {aka long long
unsigned int}’ [-Werror=format=]
qemu_log("%d@%zd.%06zd:smmuv3_find_ste_2lvl "
"strtab_base:0x%lx l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64"
l2_off:0x%x max_l2_ste:%d" "\n",
^
size_t arguments need %zx, not %lx, and uint64_t arguments need
%"PRIx64", not %lx. I'll squash in the changes to the relevant patches.
thanks
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2018-05-04 17:58 ` Peter Maydell
@ 2018-05-06 16:00 ` Auger Eric
0 siblings, 0 replies; 13+ messages in thread
From: Auger Eric @ 2018-05-06 16:00 UTC (permalink / raw)
To: Peter Maydell, QEMU Developers
Hi Peter,
On 05/04/2018 07:58 PM, Peter Maydell wrote:
> On 4 May 2018 at 18:15, Peter Maydell <peter.maydell@linaro.org> wrote:
>> target-arm queue: Eric's SMMUv3 patchset, and an array
>> of minor bugfixes and improvements from various others.
>>
>> thanks
>> -- PMM
>>
>> The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:
>>
>> Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100)
>>
>> are available in the Git repository at:
>>
>> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180504
>>
>> for you to fetch changes up to 5680740c92993e9b3f3e011f2a2c394070e33f56:
>>
>> hw/arm/virt: Introduce the iommu option (2018-05-04 18:05:52 +0100)
>>
>> ----------------------------------------------------------------
>> target-arm queue:
>> * Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board
>> if the commandline includes "-machine iommu=smmuv3"
>> * target/arm: Implement v8M VLLDM and VLSTM
>> * hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
>> * Some fixes to silence Coverity false-positives
>> * arm: boot: set boot_info starting from first_cpu
>> (fixes a technical bug not visible in practice)
>> * hw/net/smc91c111: Convert away from old_mmio
>> * hw/usb/tusb6010: Convert away from old_mmio
>> * hw/char/cmsdk-apb-uart.c: Accept more input after character read
>> * target/arm: Make MPUIR write-ignored on OMAP, StrongARM
>> * hw/arm/virt: Add linux,pci-domain property
>
> Oops, 32-bit compile failures for format string issues;
>
> hw/arm/trace.h: In function ‘_nocheck__trace_smmu_ptw_level’:
> hw/arm/trace.h:215:18: error: format ‘%lx’ expects argument of type
> ‘long unsigned int’, but argument 7 has type ‘size_t {aka unsigned
> int}’ [-Werror=format=]
> qemu_log("%d@%zd.%06zd:smmu_ptw_level " "level=%d
> iova=0x%"PRIx64" subpage_sz=0x%lx baseaddr=0x%"PRIx64" offset=%d =>
> pte=0x%"PRIx64 "\n",
> ^
> hw/arm/trace.h: In function ‘_nocheck__trace_smmuv3_write_mmio_idr’:
> hw/arm/trace.h:606:18: error: format ‘%lx’ expects argument of type
> ‘long unsigned int’, but argument 5 has type ‘uint64_t {aka long long
> unsigned int}’ [-Werror=format=]
> qemu_log("%d@%zd.%06zd:smmuv3_write_mmio_idr " "write to
> RO/Unimpl reg 0x%lx val64:0x%lx" "\n",
> ^
> hw/arm/trace.h:606:18: error: format ‘%lx’ expects argument of type
> ‘long unsigned int’, but argument 6 has type ‘uint64_t {aka long long
> unsigned int}’ [-Werror=format=]
> hw/arm/trace.h: In function ‘_nocheck__trace_smmuv3_find_ste_2lvl’:
> hw/arm/trace.h:721:18: error: format ‘%lx’ expects argument of type
> ‘long unsigned int’, but argument 5 has type ‘uint64_t {aka long long
> unsigned int}’ [-Werror=format=]
> qemu_log("%d@%zd.%06zd:smmuv3_find_ste_2lvl "
> "strtab_base:0x%lx l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64"
> l2_off:0x%x max_l2_ste:%d" "\n",
> ^
>
> size_t arguments need %zx, not %lx, and uint64_t arguments need
> %"PRIx64", not %lx. I'll squash in the changes to the relevant patches.
OK. Thank you for taking this in charge!
Eric
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/24] target-arm queue
@ 2018-01-16 13:33 Peter Maydell
2018-01-16 15:44 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2018-01-16 13:33 UTC (permalink / raw)
To: qemu-devel
More arm patches (mostly the SDHCI ones from Philippe)
thanks
-- PMM
The following changes since commit f521eeee3bd060b460c99e605472b7e03967db43:
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180116
for you to fetch changes up to 60765b6ceeb4998a0d4220b3a53f1f185061da77:
sdhci: add a 'dma' property to the sysbus devices (2018-01-16 13:28:21 +0000)
----------------------------------------------------------------
target-arm queue:
* SDHCI: cleanups and minor bug fixes
* target/arm: minor refactor preparatory to fp16 support
* omap_ssd, ssi-sd, pl181, milkymist-memcard: reset the SD
card on controller reset (fixes migration failures)
* target/arm: Handle page table walk load failures correctly
* hw/arm/virt: Add virt-2.12 machine type
* get_phys_addr_pmsav7: Support AP=0b111 for v7M
* hw/intc/armv7m: Support byte and halfword accesses to CFSR
----------------------------------------------------------------
Andrey Smirnov (1):
sdhci: Implement write method of ACMD12ERRSTS register
Peter Maydell (8):
hw/intc/armv7m: Support byte and halfword accesses to CFSR
get_phys_addr_pmsav7: Support AP=0b111 for v7M
hw/arm/virt: Add virt-2.12 machine type
target/arm: Handle page table walk load failures correctly
hw/sd/pl181: Reset SD card on controller reset
hw/sd/milkymist-memcard: Reset SD card on controller reset
hw/sd/ssi-sd: Reset SD card on controller reset
hw/sd/omap_mmc: Reset SD card on controller reset
Philippe Mathieu-Daudé (13):
sdhci: clean up includes
sdhci: remove dead code
sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties
sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init()
sdhci: refactor common sysbus/pci realize() into sdhci_common_realize()
sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize()
sdhci: use qemu_log_mask(UNIMP) instead of fprintf()
sdhci: convert the DPRINT() calls into trace events
sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h"
sdhci: rename the SDHC_CAPAB register
sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only
sdhci: fix the PCI device, using the PCI address space for DMA
sdhci: add a 'dma' property to the sysbus devices
Richard Henderson (2):
target/arm: Split out vfp_expand_imm
target/arm: Add fp16 support to vfp_expand_imm
hw/sd/sdhci-internal.h | 7 +-
include/hw/sd/sdhci.h | 19 +++-
target/arm/internals.h | 10 ++
hw/arm/virt.c | 19 +++-
hw/intc/armv7m_nvic.c | 38 ++++---
hw/sd/milkymist-memcard.c | 4 +
hw/sd/omap_mmc.c | 14 ++-
hw/sd/pl181.c | 4 +
hw/sd/sdhci.c | 266 +++++++++++++++++++++++++++------------------
hw/sd/ssi-sd.c | 25 ++++-
target/arm/helper.c | 53 ++++++++-
target/arm/op_helper.c | 7 +-
target/arm/translate-a64.c | 49 ++++++---
hw/sd/trace-events | 14 +++
14 files changed, 362 insertions(+), 167 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2018-01-16 13:33 Peter Maydell
@ 2018-01-16 15:44 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2018-01-16 15:44 UTC (permalink / raw)
To: QEMU Developers
On 16 January 2018 at 13:33, Peter Maydell <peter.maydell@linaro.org> wrote:
> More arm patches (mostly the SDHCI ones from Philippe)
>
> thanks
> -- PMM
>
> The following changes since commit f521eeee3bd060b460c99e605472b7e03967db43:
>
> Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +0000)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180116
>
> for you to fetch changes up to 60765b6ceeb4998a0d4220b3a53f1f185061da77:
>
> sdhci: add a 'dma' property to the sysbus devices (2018-01-16 13:28:21 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * SDHCI: cleanups and minor bug fixes
> * target/arm: minor refactor preparatory to fp16 support
> * omap_ssd, ssi-sd, pl181, milkymist-memcard: reset the SD
> card on controller reset (fixes migration failures)
> * target/arm: Handle page table walk load failures correctly
> * hw/arm/virt: Add virt-2.12 machine type
> * get_phys_addr_pmsav7: Support AP=0b111 for v7M
> * hw/intc/armv7m: Support byte and halfword accesses to CFSR
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/24] target-arm queue
@ 2017-04-20 16:40 Peter Maydell
2017-04-20 17:30 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2017-04-20 16:40 UTC (permalink / raw)
To: qemu-devel
First ARM pullreq of the 2.10 cycle...
thanks
-- PMM
The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:
Open 2.10 development tree (2017-04-20 15:42:31 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420
for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:
arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)
----------------------------------------------------------------
target-arm queue:
* implement M profile exception return properly
* cadence GEM: fix multiqueue handling bugs
* pxa2xx.c: QOMify a device
* arm/kvm: Remove trailing newlines from error_report()
* stellaris: Don't hw_error() on bad register accesses
* Add assertion about FSC format for syndrome registers
* Move excnames[] array into arm_log_exceptions()
* exynos: minor code cleanups
* hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
* Fix APSR writes via M profile MSR
----------------------------------------------------------------
Alistair Francis (5):
cadence_gem: Read the correct queue descriptor
cadence_gem: Correct the multi-queue can rx logic
cadence_gem: Correct the interupt logic
cadence_gem: Make the revision a property
xlnx-zynqmp: Set the Cadence GEM revision
Ard Biesheuvel (1):
hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
Ishani Chugh (1):
arm/kvm: Remove trailing newlines from error_report()
Krzysztof Kozlowski (3):
hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
hw/char/exynos4210_uart: Constify static array and few arguments
hw/misc/exynos4210_pmu: Reorder local variables for readability
Peter Maydell (13):
target/arm: Add missing entries to excnames[] for log strings
arm: Move excnames[] array into arm_log_exceptions()
target/arm: Add assertion about FSC format for syndrome registers
stellaris: Don't hw_error() on bad register accesses
arm: Don't implement BXJ on M-profile CPUs
arm: Thumb shift operations should not permit interworking branches
arm: Factor out "generate right kind of step exception"
arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
arm: Move condition-failed codepath generation out of if()
arm: Abstract out "are we singlestepping" test to utility function
arm: Track M profile handler mode state in TB flags
arm: Implement M profile exception return properly
arm: Remove workarounds for old M-profile exception return implementation
Suramya Shah (1):
hw/arm: Qomify pxa2xx.c
include/hw/net/cadence_gem.h | 1 +
target/arm/cpu.h | 10 +++
target/arm/internals.h | 21 -----
target/arm/translate.h | 5 ++
hw/arm/boot.c | 64 ++++++++++++---
hw/arm/exynos4_boards.c | 7 +-
hw/arm/pxa2xx.c | 14 ++--
hw/arm/stellaris.c | 60 ++++++++------
hw/arm/xlnx-zynqmp.c | 6 +-
hw/char/exynos4210_uart.c | 8 +-
hw/misc/exynos4210_pmu.c | 4 +-
hw/net/cadence_gem.c | 45 +++++++----
hw/timer/exynos4210_mct.c | 6 +-
hw/timer/exynos4210_pwm.c | 13 ++--
hw/timer/exynos4210_rtc.c | 19 ++---
target/arm/cpu.c | 43 +---------
target/arm/helper.c | 19 +++++
target/arm/kvm64.c | 4 +-
target/arm/op_helper.c | 23 ++++--
target/arm/translate.c | 181 +++++++++++++++++++++++++++++--------------
20 files changed, 341 insertions(+), 212 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2017-04-20 16:40 Peter Maydell
@ 2017-04-20 17:30 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2017-04-20 17:30 UTC (permalink / raw)
To: QEMU Developers
On 20 April 2017 at 17:40, Peter Maydell <peter.maydell@linaro.org> wrote:
> First ARM pullreq of the 2.10 cycle...
>
> thanks
> -- PMM
>
> The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:
>
> Open 2.10 development tree (2017-04-20 15:42:31 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420
>
> for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:
>
> arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * implement M profile exception return properly
> * cadence GEM: fix multiqueue handling bugs
> * pxa2xx.c: QOMify a device
> * arm/kvm: Remove trailing newlines from error_report()
> * stellaris: Don't hw_error() on bad register accesses
> * Add assertion about FSC format for syndrome registers
> * Move excnames[] array into arm_log_exceptions()
> * exynos: minor code cleanups
> * hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
> * Fix APSR writes via M profile MSR
>
> ----------------------------------------------------------------
> Alistair Francis (5):
> cadence_gem: Read the correct queue descriptor
> cadence_gem: Correct the multi-queue can rx logic
> cadence_gem: Correct the interupt logic
> cadence_gem: Make the revision a property
> xlnx-zynqmp: Set the Cadence GEM revision
>
> Ard Biesheuvel (1):
> hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
>
> Ishani Chugh (1):
> arm/kvm: Remove trailing newlines from error_report()
>
> Krzysztof Kozlowski (3):
> hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
> hw/char/exynos4210_uart: Constify static array and few arguments
> hw/misc/exynos4210_pmu: Reorder local variables for readability
>
> Peter Maydell (13):
> target/arm: Add missing entries to excnames[] for log strings
> arm: Move excnames[] array into arm_log_exceptions()
> target/arm: Add assertion about FSC format for syndrome registers
> stellaris: Don't hw_error() on bad register accesses
> arm: Don't implement BXJ on M-profile CPUs
> arm: Thumb shift operations should not permit interworking branches
> arm: Factor out "generate right kind of step exception"
> arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
> arm: Move condition-failed codepath generation out of if()
> arm: Abstract out "are we singlestepping" test to utility function
> arm: Track M profile handler mode state in TB flags
> arm: Implement M profile exception return properly
> arm: Remove workarounds for old M-profile exception return implementation
>
> Suramya Shah (1):
> hw/arm: Qomify pxa2xx.c
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/24] target-arm queue
@ 2015-09-14 13:52 Peter Maydell
2015-09-14 15:12 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2015-09-14 13:52 UTC (permalink / raw)
To: qemu-devel
More target-arm patches from various people.
-- PMM
The following changes since commit 2b750d9d261bda7f75b39dfc1e1e5f22502929d5:
Merge remote-tracking branch 'remotes/aurel/tags/pull-sh4-next-20150913' into staging (2015-09-14 10:46:38 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150914
for you to fetch changes up to f0d574d63f4603ec431f16ad535a555bf7548b94:
target-arm: Add VMPIDR_EL2 (2015-09-14 14:39:51 +0100)
----------------------------------------------------------------
target-arm queue:
* fix GIC region size in xlnx-zynqmp
* xlnx-zynqmp: Remove unnecessary brackets
* improve A64 generated TCG code
* add GPIO devices to i.MX25 and i.MX31
* more missing pieces for EL2 support
----------------------------------------------------------------
Alistair Francis (1):
xlnx-zynqmp: Remove unnecessary brackets around error messages
Edgar E. Iglesias (8):
hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully
target-arm: Add VTCR_EL2
target-arm: Add VTTBR_EL2
target-arm: Suppress TBI for S2 translations
target-arm: Suppress EPD for S2, EL2 and EL3 translations
target-arm: Add VPIDR_EL2
target-arm: Break out mpidr_read_val()
target-arm: Add VMPIDR_EL2
Jean-Christophe Dubois (3):
i.MX: Add GPIO device
i.MX: Add GPIO devices to i.MX31 SOC
i.MX: Add GPIO devices to i.MX25 SOC
Nathan Rossi (1):
arm: xlnx-zynqmp: Fix up GIC region size
Richard Henderson (11):
target-arm: Share all common TCG temporaries
target-arm: Introduce DisasCompare
target-arm: Handle always condition codes within arm_test_cc
target-arm: Use setcond and movcond for csel
target-arm: Implement ccmp branchless
target-arm: Implement fcsel with movcond
target-arm: Recognize SXTB, SXTH, SXTW, ASR
target-arm: Recognize UXTB, UXTH, LSR, LSL
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
target-arm: Recognize ROR
target-arm: Use tcg_gen_extrh_i64_i32
hw/arm/fsl-imx25.c | 29 ++++
hw/arm/fsl-imx31.c | 30 ++++
hw/arm/xlnx-zynqmp.c | 10 +-
hw/cpu/a15mpcore.c | 2 +-
hw/cpu/a9mpcore.c | 2 +-
hw/gpio/Makefile.objs | 1 +
hw/gpio/imx_gpio.c | 340 +++++++++++++++++++++++++++++++++++++++++++
include/hw/arm/fsl-imx25.h | 15 ++
include/hw/arm/fsl-imx31.h | 12 ++
include/hw/arm/xlnx-zynqmp.h | 2 +-
include/hw/gpio/imx_gpio.h | 62 ++++++++
target-arm/cpu.h | 4 +
target-arm/helper.c | 158 ++++++++++++++++++--
target-arm/translate-a64.c | 340 +++++++++++++++++++++++++------------------
target-arm/translate.c | 134 ++++++++++-------
target-arm/translate.h | 17 +++
16 files changed, 949 insertions(+), 209 deletions(-)
create mode 100644 hw/gpio/imx_gpio.c
create mode 100644 include/hw/gpio/imx_gpio.h
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/24] target-arm queue
2015-09-14 13:52 Peter Maydell
@ 2015-09-14 15:12 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2015-09-14 15:12 UTC (permalink / raw)
To: QEMU Developers
On 14 September 2015 at 14:52, Peter Maydell <peter.maydell@linaro.org> wrote:
> More target-arm patches from various people.
>
> -- PMM
>
> The following changes since commit 2b750d9d261bda7f75b39dfc1e1e5f22502929d5:
>
> Merge remote-tracking branch 'remotes/aurel/tags/pull-sh4-next-20150913' into staging (2015-09-14 10:46:38 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150914
>
> for you to fetch changes up to f0d574d63f4603ec431f16ad535a555bf7548b94:
>
> target-arm: Add VMPIDR_EL2 (2015-09-14 14:39:51 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * fix GIC region size in xlnx-zynqmp
> * xlnx-zynqmp: Remove unnecessary brackets
> * improve A64 generated TCG code
> * add GPIO devices to i.MX25 and i.MX31
> * more missing pieces for EL2 support
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-06-17 15:47 UTC | newest]
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