From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fFgVC-0005RU-03 for qemu-devel@nongnu.org; Mon, 07 May 2018 09:48:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fFgV7-0003iR-T3 for qemu-devel@nongnu.org; Mon, 07 May 2018 09:48:30 -0400 From: luporl Date: Mon, 7 May 2018 10:48:06 -0300 Message-Id: <20180507134806.33043-1-leandro.lupori@gmail.com> Subject: [Qemu-devel] [PATCH] Allow PIR read in privileged mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: luporl , David Gibson , Alexander Graf , qemu-ppc@nongnu.org According to PowerISA, the PIR register should be readable in privileged mode also, not only in hypervisor privileged mode. Cc: David Gibson Cc: Alexander Graf Cc: qemu-ppc@nongnu.org Signed-off-by: Leandro Lupori Reviewed-by: Jose Ricardo Ziviani --- target/ppc/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index a72be6d121..7b56e3ffb9 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -7816,7 +7816,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env) /* Processor identification */ spr_register_hv(env, SPR_PIR, "PIR", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, &spr_read_generic, NULL, 0x00000000); spr_register_hv(env, SPR_HID0, "HID0", -- 2.11.0