Re: [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

Re: [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

[Eduardo Habkost]

On Fri, May 04, 2018 at 11:57:33AM +0800, Jingqi Liu wrote:
> The CLDEMOTE instruction hints to hardware that the cache line that
> contains the linear address should be moved("demoted") from
> the cache(s) closest to the processor core to a level more distant
> from the processor core. This may accelerate subsequent accesses
> to the line by other cores in the same coherence domain,
> especially if the line was written by the core that demotes the line.
> 
> Intel Snow Ridge has added new cpu feature, CLDEMOTE.
> The new cpu feature needs to be exposed to guest VM.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>

Thanks.  Do you have a pointer to the corresponding
GET_SUPPORTED_CPUID patch in KVM?

-- 
Eduardo

Re: [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

[Liu, Jingqi]

Yes.  The corresponding patch in KVM refers to the following link:
https://www.spinics.net/lists/kernel/msg2792864.html
Thanks.

-----Original Message-----
From: Eduardo Habkost [mailto:ehabkost@redhat.com] 
Sent: Thursday, May 3, 2018 11:05 AM
To: Liu, Jingqi <jingqi.liu@intel.com>
Cc: qemu-devel@nongnu.org; pbonzini@redhat.com; rth@twiddle.net
Subject: Re: [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

On Fri, May 04, 2018 at 11:57:33AM +0800, Jingqi Liu wrote:
> The CLDEMOTE instruction hints to hardware that the cache line that 
> contains the linear address should be moved("demoted") from the 
> cache(s) closest to the processor core to a level more distant from 
> the processor core. This may accelerate subsequent accesses to the 
> line by other cores in the same coherence domain, especially if the 
> line was written by the core that demotes the line.
> 
> Intel Snow Ridge has added new cpu feature, CLDEMOTE.
> The new cpu feature needs to be exposed to guest VM.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>

Thanks.  Do you have a pointer to the corresponding GET_SUPPORTED_CPUID patch in KVM?

--
Eduardo

[Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

[Jingqi Liu]

The CLDEMOTE instruction hints to hardware that the cache line that
contains the linear address should be moved("demoted") from
the cache(s) closest to the processor core to a level more distant
from the processor core. This may accelerate subsequent accesses
to the line by other cores in the same coherence domain,
especially if the line was written by the core that demotes the line.

Intel Snow Ridge has added new cpu feature, CLDEMOTE.
The new cpu feature needs to be exposed to guest VM.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ec1efd3..d5a5abf 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -483,7 +483,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
             "la57", NULL, NULL, NULL,
             NULL, NULL, "rdpid", NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, "cldemote", NULL, NULL,
             NULL, NULL, NULL, NULL,
         },
         .cpuid_eax = 7,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0c3f514..3ef90e0 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -678,6 +678,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
 #define CPUID_7_0_ECX_LA57     (1U << 16)
 #define CPUID_7_0_ECX_RDPID    (1U << 22)
+#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */
 
 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

[Eduardo Habkost]

On Fri, May 04, 2018 at 11:57:33AM +0800, Jingqi Liu wrote:
> The CLDEMOTE instruction hints to hardware that the cache line that
> contains the linear address should be moved("demoted") from
> the cache(s) closest to the processor core to a level more distant
> from the processor core. This may accelerate subsequent accesses
> to the line by other cores in the same coherence domain,
> especially if the line was written by the core that demotes the line.
> 
> Intel Snow Ridge has added new cpu feature, CLDEMOTE.
> The new cpu feature needs to be exposed to guest VM.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>

Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>

Queued, thanks.

> ---
>  target/i386/cpu.c | 2 +-
>  target/i386/cpu.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ec1efd3..d5a5abf 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -483,7 +483,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>              "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
>              "la57", NULL, NULL, NULL,
>              NULL, NULL, "rdpid", NULL,
> -            NULL, NULL, NULL, NULL,
> +            NULL, "cldemote", NULL, NULL,
>              NULL, NULL, NULL, NULL,
>          },
>          .cpuid_eax = 7,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 0c3f514..3ef90e0 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -678,6 +678,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
>  #define CPUID_7_0_ECX_LA57     (1U << 16)
>  #define CPUID_7_0_ECX_RDPID    (1U << 22)
> +#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */
>  
>  #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
>  #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
> -- 
> 1.8.3.1
> 
> 

-- 
Eduardo