From: Eduardo Habkost <ehabkost@redhat.com>
To: Babu Moger <babu.moger@amd.com>
Cc: mst@redhat.com, marcel@redhat.com, pbonzini@redhat.com,
rth@twiddle.net, mtosatti@redhat.com, geoff@hostfission.com,
kash@tripleback.net, qemu-devel@nongnu.org, kvm@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH v7 1/9] i386: Helpers to encode cache information consistently
Date: Mon, 7 May 2018 16:05:01 -0300 [thread overview]
Message-ID: <20180507190501.GA13350@localhost.localdomain> (raw)
In-Reply-To: <1524760009-24710-2-git-send-email-babu.moger@amd.com>
Hi,
I was about to apply this because I assumed it was the same patch
I sent in March, but then I found this:
On Thu, Apr 26, 2018 at 11:26:41AM -0500, Babu Moger wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Instead of having a collection of macros that need to be used in
> complex expressions to build CPUID data, define a CPUCacheInfo
> struct that can hold information about a given cache. Helper
> functions will take a CPUCacheInfo struct as input to encode
> CPUID leaves for a cache.
>
> This will help us ensure consistency between cache information
> CPUID leaves, and make the existing inconsistencies in CPUID info
> more visible.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Tested-by: Geoffrey McRae <geoff@hostfission.com>
[...]
> -#define L2_ASSOCIATIVITY 16
[...]
> /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
> +static CPUCacheInfo l2_cache_amd = {
[...]
> + .associativity = 8,
[...]
> +};
[...]
> case 0x80000006:
[...]
> - *ecx = (L2_SIZE_KB_AMD << 16) | \
> - (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
> - (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
[...]
> + encode_cache_cpuid80000006(&l2_cache_amd,
> + cpu->enable_l3_cache ? &l3_cache : NULL,
> + ecx, edx);
[...]
The structs added by this patch are supposed to represent the
legacy cache sizes, and must match the old code. My original
patch set l2_cache_amd.associativity=16 because of that.
This patch changes 0x80000006 from associativity=16 to
associativity=8. Why?
--
Eduardo
next prev parent reply other threads:[~2018-05-07 19:05 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-26 16:26 [Qemu-devel] [PATCH v7 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU Babu Moger
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 1/9] i386: Helpers to encode cache information consistently Babu Moger
2018-05-07 19:05 ` Eduardo Habkost [this message]
2018-05-07 21:14 ` Moger, Babu
2018-05-07 21:27 ` Eduardo Habkost
2018-05-07 22:47 ` Moger, Babu
2018-05-08 18:40 ` Moger, Babu
2018-05-08 19:07 ` Eduardo Habkost
2018-05-08 19:34 ` Moger, Babu
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 2/9] i386: Add cache information in X86CPUDefinition Babu Moger
2018-05-07 19:09 ` Eduardo Habkost
2018-05-07 22:56 ` Moger, Babu
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 3/9] i386: Initialize cache information for EPYC family processors Babu Moger
2018-05-07 20:22 ` Eduardo Habkost
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 4/9] i386: Add new property to control cache info Babu Moger
2018-05-07 19:14 ` Eduardo Habkost
2018-05-07 23:29 ` Moger, Babu
2018-05-08 14:25 ` Eduardo Habkost
2018-05-08 17:26 ` Moger, Babu
2018-05-08 18:33 ` Eduardo Habkost
2018-05-08 18:44 ` Moger, Babu
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 5/9] i386: Use the statically loaded cache definitions Babu Moger
2018-05-07 19:15 ` Eduardo Habkost
2018-05-07 23:32 ` Moger, Babu
2018-05-07 19:37 ` Eduardo Habkost
2018-05-07 23:39 ` Moger, Babu
2018-05-08 14:12 ` Eduardo Habkost
2018-05-08 17:08 ` Moger, Babu
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D Babu Moger
2018-05-07 21:06 ` Eduardo Habkost
2018-05-08 16:41 ` Moger, Babu
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 7/9] i386: Add support for CPUID_8000_001E for AMD Babu Moger
2018-05-07 19:39 ` Eduardo Habkost
2018-05-07 23:44 ` Moger, Babu
2018-05-08 14:16 ` Eduardo Habkost
2018-05-08 15:02 ` Moger, Babu
2018-05-11 14:12 ` Eduardo Habkost
2018-05-11 14:44 ` Moger, Babu
2018-05-11 14:59 ` Eduardo Habkost
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU Babu Moger
2018-05-07 21:07 ` Eduardo Habkost
2018-04-26 16:26 ` [Qemu-devel] [PATCH v7 9/9] i386: Remove generic SMT thread check Babu Moger
2018-05-07 21:14 ` Eduardo Habkost
2018-04-26 20:49 ` [Qemu-devel] [PATCH v7 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU geoff
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