qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	frederic.konrad@adacore.com, alistair@alistair23.me,
	frasse.iglesias@gmail.com, sai.pavan.boddu@xilinx.com,
	edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PATCH v2 12/36] target-microblaze: Remove pointer indirection for ld/st addresses
Date: Tue,  8 May 2018 19:31:28 +0200	[thread overview]
Message-ID: <20180508173152.29327-13-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <20180508173152.29327-1-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index daed0b7e1f..5cc53eb035 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -848,7 +848,7 @@ static void dec_imm(DisasContext *dc)
     dc->clear_imm = 0;
 }
 
-static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
+static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t)
 {
     bool extimm = dc->tb_flags & IMM_FLAG;
     /* Should be set to true if r1 is used by loadstores.  */
@@ -863,10 +863,10 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
     if (!dc->type_b) {
         /* If any of the regs is r0, return the value of the other reg.  */
         if (dc->ra == 0) {
-            tcg_gen_mov_i32(*t, cpu_R[dc->rb]);
+            tcg_gen_mov_i32(t, cpu_R[dc->rb]);
             return;
         } else if (dc->rb == 0) {
-            tcg_gen_mov_i32(*t, cpu_R[dc->ra]);
+            tcg_gen_mov_i32(t, cpu_R[dc->ra]);
             return;
         }
 
@@ -874,27 +874,27 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
             stackprot = true;
         }
 
-        tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
+        tcg_gen_add_i32(t, cpu_R[dc->ra], cpu_R[dc->rb]);
 
         if (stackprot) {
-            gen_helper_stackprot(cpu_env, *t);
+            gen_helper_stackprot(cpu_env, t);
         }
         return;
     }
     /* Immediate.  */
     if (!extimm) {
         if (dc->imm == 0) {
-            tcg_gen_mov_i32(*t, cpu_R[dc->ra]);
+            tcg_gen_mov_i32(t, cpu_R[dc->ra]);
             return;
         }
-        tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm));
-        tcg_gen_add_i32(*t, cpu_R[dc->ra], *t);
+        tcg_gen_movi_i32(t, (int32_t)((int16_t)dc->imm));
+        tcg_gen_add_i32(t, cpu_R[dc->ra], t);
     } else {
-        tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
+        tcg_gen_add_i32(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
     }
 
     if (stackprot) {
-        gen_helper_stackprot(cpu_env, *t);
+        gen_helper_stackprot(cpu_env, t);
     }
     return;
 }
@@ -929,7 +929,7 @@ static void dec_load(DisasContext *dc)
 
     t_sync_flags(dc);
     addr = tcg_temp_new_i32();
-    compute_ldst_addr(dc, &addr);
+    compute_ldst_addr(dc, addr);
 
     /*
      * When doing reverse accesses we need to do two things.
@@ -1041,7 +1041,7 @@ static void dec_store(DisasContext *dc)
     sync_jmpstate(dc);
     /* SWX needs a temp_local.  */
     addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32();
-    compute_ldst_addr(dc, &addr);
+    compute_ldst_addr(dc, addr);
 
     if (ex) { /* swx */
         TCGv_i32 tval;
-- 
2.14.1

  parent reply	other threads:[~2018-05-08 17:32 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-08 17:31 [Qemu-devel] [PATCH v2 00/36] target-microblaze: Add support for Extended Addressing Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 01/36] target-microblaze: dec_load: Use bool instead of unsigned int Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 02/36] target-microblaze: dec_store: " Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 03/36] target-microblaze: compute_ldst_addr: Use bool instead of int Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 04/36] target-microblaze: Fallback to our latest CPU version Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 05/36] target-microblaze: Correct special register array sizes Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 06/36] target-microblaze: Correct the PVR array size Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 07/36] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 08/36] target-microblaze: Remove USE_MMU PVR checks Edgar E. Iglesias
2018-05-09 20:48   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 09/36] target-microblaze: Conditionalize setting of PVR11_USE_MMU Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 10/36] target-microblaze: Bypass MMU with MMU_NOMMU_IDX Edgar E. Iglesias
2018-05-09 20:51   ` Richard Henderson
2018-05-15 21:45     ` Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 11/36] target-microblaze: Make compute_ldst_addr always use a temp Edgar E. Iglesias
2018-05-08 17:31 ` Edgar E. Iglesias [this message]
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 13/36] target-microblaze: Use TCGv for load/store addresses Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 14/36] target-microblaze: Name special registers we support Edgar E. Iglesias
2018-05-09 20:57   ` Alistair Francis
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 15/36] target-microblaze: Break out trap_userspace() Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 16/36] target-microblaze: Break out trap_illegal() Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 17/36] target-microblaze: dec_msr: Use bool and extract32 Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 18/36] target-microblaze: dec_msr: Reuse more code when reg-decoding Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 19/36] target-microblaze: dec_msr: Fix MTS to FSR Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 20/36] target-microblaze: Make special registers 64-bit Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 21/36] target-microblaze: Setup for 64bit addressing Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 23/36] target-microblaze: Implement MFSE EAR Edgar E. Iglesias
2018-05-09 21:04   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 24/36] target-microblaze: mmu: Add R_TBLX_MISS macros Edgar E. Iglesias
2018-05-09 21:09   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 25/36] target-microblaze: mmu: Remove unused register state Edgar E. Iglesias
2018-05-09 21:10   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 26/36] target-microblaze: mmu: Prepare for 64-bit addresses Edgar E. Iglesias
2018-05-09 21:11   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 27/36] target-microblaze: mmu: Add a configurable output address mask Edgar E. Iglesias
2018-05-09 21:12   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 28/36] target-microblaze: Add support for extended access to TLBLO Edgar E. Iglesias
2018-05-09 21:15   ` Richard Henderson
2018-05-15 22:23     ` Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 29/36] target-microblaze: Allow address sizes between 32 and 64 bits Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 30/36] target-microblaze: Simplify address computation using tcg_gen_addi_i32() Edgar E. Iglesias
2018-05-09 21:16   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 31/36] target-microblaze: mmu: Cleanup debug log messages Edgar E. Iglesias
2018-05-09 21:16   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 32/36] target-microblaze: Use table based condition-codes conversion Edgar E. Iglesias
2018-05-09 21:18   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 33/36] target-microblaze: Remove argument b in eval_cc() Edgar E. Iglesias
2018-05-09 21:18   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 34/36] target-microblaze: Convert env_btaken to i64 Edgar E. Iglesias
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 35/36] target-microblaze: Convert env_btarget " Edgar E. Iglesias
2018-05-09 21:20   ` Richard Henderson
2018-05-08 17:31 ` [Qemu-devel] [PATCH v2 36/36] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp Edgar E. Iglesias
2018-05-09 21:21   ` Richard Henderson
2018-05-16 18:49     ` Edgar E. Iglesias
     [not found] ` <20180508173152.29327-23-edgar.iglesias@gmail.com>
2018-05-09 21:09   ` [Qemu-devel] [PATCH v2 22/36] target-microblaze: Add Extended Addressing Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180508173152.29327-13-edgar.iglesias@gmail.com \
    --to=edgar.iglesias@gmail.com \
    --cc=alistair@alistair23.me \
    --cc=edgar.iglesias@xilinx.com \
    --cc=frasse.iglesias@gmail.com \
    --cc=frederic.konrad@adacore.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=sai.pavan.boddu@xilinx.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).