From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 21/21] target/arm: Clear SVE high bits for FMOV
Date: Thu, 10 May 2018 18:45:19 +0100 [thread overview]
Message-ID: <20180510174519.11264-22-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180510174519.11264-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.
Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180502221552.3873-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b302171545..b0471c842e 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5681,31 +5681,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
if (itof) {
TCGv_i64 tcg_rn = cpu_reg(s, rn);
+ TCGv_i64 tmp;
switch (type) {
case 0:
- {
/* 32 bit */
- TCGv_i64 tmp = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
tcg_gen_ext32u_i64(tmp, tcg_rn);
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
- tcg_gen_movi_i64(tmp, 0);
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
+ write_fp_dreg(s, rd, tmp);
tcg_temp_free_i64(tmp);
break;
- }
case 1:
- {
/* 64 bit */
- TCGv_i64 tmp = tcg_const_i64(0);
- tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
- tcg_temp_free_i64(tmp);
+ write_fp_dreg(s, rd, tcg_rn);
break;
- }
case 2:
/* 64 bit to top half. */
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
+ clear_vec_high(s, true, rd);
break;
}
} else {
--
2.17.0
next prev parent reply other threads:[~2018-05-10 17:45 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-10 17:44 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2018-05-10 17:44 ` [Qemu-devel] [PULL 01/21] hw/arm/iotkit.c: fix minor memory leak Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 02/21] softfloat: Handle default NaN mode after pickNaNMulAdd, not before Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 03/21] pc: simplify MachineClass::get_hotplug_handler handling Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 04/21] platform-bus-device: use device plug callback instead of machine_done notifier Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 05/21] arm/boot: split load_dtb() from arm_load_kernel() Peter Maydell
2018-05-23 7:38 ` Auger Eric
2018-05-23 10:25 ` Igor Mammedov
2018-05-10 17:45 ` [Qemu-devel] [PULL 06/21] make sure that we aren't overwriting mc->get_hotplug_handler by accident Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 07/21] atomic.h: Work around gcc spurious "unused value" warning Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 08/21] tcg: Introduce helpers for integer min/max Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 09/21] target/arm: Use new min/max expanders Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 10/21] target/xtensa: " Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 11/21] tcg: Introduce atomic helpers for integer min/max Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 12/21] tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 13/21] target/riscv: Use new atomic min/max expanders Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 14/21] target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 15/21] target/arm: Fill in disas_ldst_atomic Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 16/21] target/arm: Implement CAS and CASP Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 17/21] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 18/21] target/arm: Implement vector shifted SCVF/UCVF for fp16 Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 19/21] target/arm: Implement vector shifted FCVT " Peter Maydell
2018-05-10 17:45 ` [Qemu-devel] [PULL 20/21] target/arm: Fix float16 to/from int16 Peter Maydell
2018-05-10 17:45 ` Peter Maydell [this message]
2018-05-10 18:06 ` [Qemu-devel] [PULL 00/21] target-arm queue no-reply
2018-05-14 8:46 ` Peter Maydell
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