[Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

[Richard Henderson <richard.henderson@linaro.org>]

Cc: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/fpu_helper.c | 6 ++++++
 target/riscv/op_helper.c  | 3 +--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3..f2bc243b95 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -265,6 +265,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
                                           uint32_t exception, uintptr_t pc);
 
 target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
+target_ulong cpu_riscv_get_fcsr(CPURISCVState *env);
 void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
 
 #define TB_FLAGS_MMU_MASK  3
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index abbadead5c..41c7352115 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -37,6 +37,12 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
     return hard;
 }
 
+target_ulong cpu_riscv_get_fcsr(CPURISCVState *env)
+{
+    return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
+         | (env->frm << FSR_RD_SHIFT);
+}
+
 void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
 {
     int soft = 0;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3abf52453c..fd2d8c0a9d 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -423,8 +423,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
         return env->frm;
     case CSR_FCSR:
         validate_mstatus_fs(env, GETPC());
-        return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
-                | (env->frm << FSR_RD_SHIFT);
+        return cpu_riscv_get_fcsr(env);
     /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
 #ifdef CONFIG_USER_ONLY
     case CSR_TIME:
-- 
2.17.0