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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Stafford Horne <shorne@gmail.com>, peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 13/13] target/openrisc: Merge disas_openrisc_insn
Date: Mon, 14 May 2018 15:27:14 -0700	[thread overview]
Message-ID: <20180514222714.7982-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180514222714.7982-1-richard.henderson@linaro.org>

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/translate.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 1f87ad6b2e..e7c96ca990 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1373,14 +1373,6 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn)
     return true;
 }
 
-static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
-{
-    uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
-    if (!decode(dc, insn)) {
-        gen_illegal_exception(dc);
-    }
-}
-
 static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
 {
     DisasContext *dc = container_of(dcb, DisasContext, base);
@@ -1435,8 +1427,11 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+    uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
 
-    disas_openrisc_insn(dc, cpu);
+    if (!decode(dc, insn)) {
+        gen_illegal_exception(dc);
+    }
     dc->base.pc_next += 4;
 
     /* delay slot */
-- 
2.17.0

  parent reply	other threads:[~2018-05-14 22:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-14 22:27 [Qemu-devel] [PULL v2 00/13] target/openrisc: Covert to decodetree.py Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 01/13] target-openrisc: Write back result before FPE exception Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 02/13] target/openrisc: Start conversion to decodetree.py Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 03/13] target/openrisc: Convert branch insns Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 04/13] target/openrisc: Convert memory insns Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 05/13] target/openrisc: Convert remainder of dec_misc insns Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 06/13] target/openrisc: Convert dec_calc Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 07/13] target/openrisc: Convert dec_mac Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 08/13] target/openrisc: Convert dec_logic Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 09/13] target/openrisc: Convert dec_M Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 10/13] target/openrisc: Convert dec_comp Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 11/13] target/openrisc: Convert dec_compi Richard Henderson
2018-05-14 22:27 ` [Qemu-devel] [PULL 12/13] target/openrisc: Convert dec_float Richard Henderson
2018-05-14 22:27 ` Richard Henderson [this message]
2018-05-15 11:00 ` [Qemu-devel] [PULL v2 00/13] target/openrisc: Covert to decodetree.py Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2018-05-11  4:23 [Qemu-devel] [PULL 00/13] openrisc: " Richard Henderson
2018-05-11  4:23 ` [Qemu-devel] [PULL 13/13] target/openrisc: Merge disas_openrisc_insn Richard Henderson

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