From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <rth@twiddle.net>,
Eduardo Habkost <ehabkost@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
qemu-devel@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>,
Babu Moger <babu.moger@amd.com>
Subject: [Qemu-devel] [PULL 4/7] i386: Add cache information in X86CPUDefinition
Date: Tue, 15 May 2018 18:54:33 -0300 [thread overview]
Message-ID: <20180515215436.6457-5-ehabkost@redhat.com> (raw)
In-Reply-To: <20180515215436.6457-1-ehabkost@redhat.com>
From: Babu Moger <babu.moger@amd.com>
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20180510204148.11687-3-babu.moger@amd.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 7 +++++++
target/i386/cpu.c | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 512c69dddd..ac94013c4a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1097,6 +1097,12 @@ typedef struct CPUCacheInfo {
} CPUCacheInfo;
+typedef struct CPUCaches {
+ CPUCacheInfo l1d_cache;
+ CPUCacheInfo l1i_cache;
+ CPUCacheInfo l2_cache;
+ CPUCacheInfo l3_cache;
+} CPUCaches;
typedef struct CPUX86State {
/* standard registers */
@@ -1286,6 +1292,7 @@ typedef struct CPUX86State {
/* Features that were explicitly enabled/disabled */
FeatureWordArray user_features;
uint32_t cpuid_model[12];
+ CPUCaches *cache_info;
/* MTRRs */
uint64_t mtrr_fixed[11];
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 28bb93990e..55685ed19d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1106,6 +1106,7 @@ struct X86CPUDefinition {
int stepping;
FeatureWordArray features;
const char *model_id;
+ CPUCaches *cache_info;
};
static X86CPUDefinition builtin_x86_defs[] = {
--
2.14.3
next prev parent reply other threads:[~2018-05-15 21:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-15 21:54 [Qemu-devel] [PULL 0/7] x86 queue, 2018-05-15 Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 1/7] i386: add KnightsMill cpu model Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 2/7] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 3/7] i386: Helpers to encode cache information consistently Eduardo Habkost
2018-05-15 21:54 ` Eduardo Habkost [this message]
2018-05-15 21:54 ` [Qemu-devel] [PULL 5/7] i386: Initialize cache information for EPYC family processors Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 6/7] pc: add 2.13 machine types Eduardo Habkost
2018-05-15 21:54 ` [Qemu-devel] [PULL 7/7] i386: Add new property to control cache info Eduardo Habkost
2018-05-17 10:09 ` [Qemu-devel] [PULL 0/7] x86 queue, 2018-05-15 Peter Maydell
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