From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41957) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIyjl-0004Tu-E7 for qemu-devel@nongnu.org; Wed, 16 May 2018 11:53:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIyjj-000558-KC for qemu-devel@nongnu.org; Wed, 16 May 2018 11:53:09 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:40499) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIyjj-00054y-EW for qemu-devel@nongnu.org; Wed, 16 May 2018 11:53:07 -0400 Received: by mail-pl0-x242.google.com with SMTP id t12-v6so667440plo.7 for ; Wed, 16 May 2018 08:53:07 -0700 (PDT) From: Richard Henderson Date: Wed, 16 May 2018 08:52:29 -0700 Message-Id: <20180516155243.16937-15-richard.henderson@linaro.org> In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 14/28] target/arm: Remove floatX_maybe_silence_nan from conversions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org This is now handled properly by the generic softfloat code. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6f0eb83661..f92bdea732 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r = float64_to_float32(a, &tstat); - r = float32_maybe_silence_nan(r, &tstat); exflags = get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r = make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index e05c7230d4..db8bbe52a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r = float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r = float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } /* VFP3 fixed point conversion. */ -- 2.17.0