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From: David Gibson <david@gibson.dropbear.id.au>
To: luporl <leandro.lupori@gmail.com>
Cc: qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>,
	qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode
Date: Mon, 4 Jun 2018 10:53:22 +1000	[thread overview]
Message-ID: <20180604005322.GE4251@umbus> (raw)
In-Reply-To: <20180507165242.46502-1-leandro.lupori@gmail.com>

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On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote:
> According to PowerISA, the PIR register should be readable in privileged
> mode also, not only in hypervisor privileged mode.
> 
> PowerISA 3.0 - 4.3.3 Processor Identification Register
> 
> "Read access to the PIR is privileged; write access is not
> provided."

Yes... but a little further down it says "The PIR is a hypervisor
resource".  Looking at the older 2.07 ISA, it says that
guest-supervisor mode reads to the PIR should be redirected to the
GPIR register, which this change won't accomplish.

So, I'm not sure what to make of this.

> 
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-ppc@nongnu.org
> Signed-off-by: Leandro Lupori <leandro.lupori@gmail.com>
> Reviewed-by: Jose Ricardo Ziviani <joserz@linux.ibm.com>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> ---
> Changes in v2:
> - added my Signed-off-by, maintainers CC and Jose's Reviewed-by tags
> 
> Changes in v3:
> - added subsystem name, version tag and summary of changes
> - added the section of PowerISA that describes PIR access privileges
> 
>  target/ppc/translate_init.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index a72be6d121..7b56e3ffb9 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -7816,7 +7816,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
>      /* Processor identification */
>      spr_register_hv(env, SPR_PIR, "PIR",
>                   SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, SPR_NOACCESS,
>                   &spr_read_generic, NULL,
>                   0x00000000);
>      spr_register_hv(env, SPR_HID0, "HID0",

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2018-06-04  1:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-07 13:48 [Qemu-devel] [PATCH] Allow PIR read in privileged mode luporl
2018-05-07 16:08 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2018-05-07 16:52   ` [Qemu-devel] [PATCH v3] target/ppc: " luporl
2018-06-04  0:53     ` David Gibson [this message]
2018-06-05 16:46       ` Greg Kurz
2018-06-06  0:53         ` David Gibson
2018-06-06  9:19           ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2018-06-08  9:20             ` David Gibson

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