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Date: Mon, 4 Jun 2018 16:20:53 -0400
From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Message-ID: <20180604202053.GG5867@char.us.oracle.com>
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Subject: Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID
 feature bit
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To: Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= <berrange@redhat.com>
Cc: pbonzini@redhat.com, rth@twiddle.net, qemu-devel@nongnu.org, kvm@vger.kernel.org, ehabkost@redhat.com

On Mon, Jun 04, 2018 at 09:54:40AM +0100, Daniel P. Berrang=E9 wrote:
> On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote:
> > AMD future CPUs expose _two_ ways to utilize the Intel equivalant
> > of the Speculative Store Bypass Disable. The first is via
> > the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
> > is via the SPEC_CTRL MSR (0x48). The document titled:
> > 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> >=20
> > gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
> >=20
> > A copy of this document is available at
> >       https://bugzilla.kernel.org/show_bug.cgi?id=3D199889
> >=20
> > Anyhow, this means that on future AMD CPUs there will be  _two_ ways =
to
> > deal with SSBD.
>=20
> Oh what fun ;-)
>=20
> Unless I'm mistaken the current Linux kernel doesn't know about these
> new amd-ssbd / amd-no-ssb flags either. Will you also be sending patche=
s
> for that half of the problem ?

I sent them as well. But forgot to CC qemu-devel :-(