From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQUnJ-0001ix-3n for qemu-devel@nongnu.org; Wed, 06 Jun 2018 05:31:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQUnI-0003jt-4n for qemu-devel@nongnu.org; Wed, 06 Jun 2018 05:31:53 -0400 From: luc.michel@greensocs.com Date: Wed, 6 Jun 2018 11:30:57 +0200 Message-Id: <20180606093101.30518-3-luc.michel@greensocs.com> In-Reply-To: <20180606093101.30518-1-luc.michel@greensocs.com> References: <20180606093101.30518-1-luc.michel@greensocs.com> Subject: [Qemu-devel] [PATCH 2/6] intc/arm_gic: Remove some dead code and put some functions static List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Luc MICHEL , qemu-arm@nongnu.org, Peter Maydell , saipava@xilinx.com, edgari@xilinx.com, mark.burton@greensocs.com, Jan Kiszka From: Luc MICHEL Some functions are now only used in arm_gic.c, put them static. Some of them where only used by the NVIC implementation and are not used anymore, so remove them. Signed-off-by: Luc MICHEL --- hw/intc/arm_gic.c | 23 ++--------------------- hw/intc/gic_internal.h | 4 ---- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 141f3e7a48..679b19fb94 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -71,7 +71,7 @@ static inline bool gic_has_groups(GICState *s) /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed. */ -void gic_update(GICState *s) +static void gic_update(GICState *s) { int best_irq; int best_prio; @@ -137,19 +137,6 @@ void gic_update(GICState *s) } } -void gic_set_pending_private(GICState *s, int cpu, int irq) -{ - int cm = 1 << cpu; - - if (gic_test_pending(s, irq, cm)) { - return; - } - - DPRINTF("Set %d pending cpu %d\n", irq, cpu); - GIC_DIST_SET_PENDING(irq, cm); - gic_update(s); -} - static void gic_set_irq_11mpcore(GICState *s, int irq, int level, int cm, int target) { @@ -565,7 +552,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) GIC_DIST_CLEAR_ACTIVE(irq, cm); } -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) +static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) { int cm = 1 << cpu; int group; @@ -1418,12 +1405,6 @@ static const MemoryRegionOps gic_cpu_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -/* This function is used by nvic model */ -void gic_init_irqs_and_distributor(GICState *s) -{ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); -} - static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 6f8d242904..a2075a94db 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -75,11 +75,7 @@ /* The special cases for the revision property: */ #define REV_11MPCORE 0 -void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs); -void gic_update(GICState *s); -void gic_init_irqs_and_distributor(GICState *s); void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs); -- 2.17.0