[Qemu-devel] [PATCH v4 25/28] spapr: fix XICS migration

["Cédric Le Goater" <clg@kaod.org>]

Extend the sPAPR IRQ backend with a new handler to handle XICS
post_load() specificities.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/spapr_irq.h |  1 +
 hw/ppc/spapr.c             |  9 ++-------
 hw/ppc/spapr_irq.c         | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index 85829928a9c4..1ca35ffc13cd 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -47,6 +47,7 @@ typedef struct sPAPRIrq {
                         void *fdt, uint32_t phandle);
     Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
                                Error **errp);
+    void (*post_load)(sPAPRMachineState *spapr);
 } sPAPRIrq;
 
 extern sPAPRIrq spapr_irq_legacy;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2774b53f169e..025d5af84def 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1689,6 +1689,7 @@ static int spapr_pre_load(void *opaque)
 static int spapr_post_load(void *opaque, int version_id)
 {
     sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
+    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
     int err = 0;
 
     err = spapr_caps_post_migration(spapr);
@@ -1696,13 +1697,7 @@ static int spapr_post_load(void *opaque, int version_id)
         return err;
     }
 
-    if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
-        CPUState *cs;
-        CPU_FOREACH(cs) {
-            PowerPCCPU *cpu = POWERPC_CPU(cs);
-            icp_resend(ICP(cpu->intc));
-        }
-    }
+    smc->irq->post_load(spapr);
 
     /* In earlier versions, there was no separate qdev for the PAPR
      * RTC, so the RTC offset was stored directly in sPAPREnvironment.
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index a5d89c6ac55f..5f445e17d125 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -254,6 +254,17 @@ static Object *spapr_irq_cpu_intc_create_legacy(sPAPRMachineState *spapr,
     return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
 }
 
+static void spapr_irq_post_load_legacy(sPAPRMachineState *spapr)
+{
+    if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
+        CPUState *cs;
+        CPU_FOREACH(cs) {
+            PowerPCCPU *cpu = POWERPC_CPU(cs);
+            icp_resend(ICP(cpu->intc));
+        }
+    }
+}
+
 sPAPRIrq spapr_irq_legacy = {
     .nr_irqs     = XICS_IRQS_SPAPR,
     .ov5         = 0x0, /* XICS only */
@@ -266,6 +277,7 @@ sPAPRIrq spapr_irq_legacy = {
     .print_info  = spapr_irq_print_info_legacy,
     .dt_populate = spapr_irq_dt_populate_legacy,
     .cpu_intc_create = spapr_irq_cpu_intc_create_legacy,
+    .post_load   = spapr_irq_post_load_legacy,
 };
 
 /*
@@ -487,6 +499,11 @@ static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
     return spapr_irq_cpu_intc_create_legacy(spapr, cpu, errp);
 }
 
+static void spapr_irq_post_load_xics(sPAPRMachineState *spapr)
+{
+    spapr_irq_post_load_legacy(spapr);
+}
+
 /*
  * XICS IRQ number space
  *
@@ -534,6 +551,7 @@ sPAPRIrq spapr_irq_xics = {
     .print_info  = spapr_irq_print_info_xics,
     .dt_populate = spapr_irq_dt_populate_xics,
     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
+    .post_load   = spapr_irq_post_load_xics,
 };
 
 /*
@@ -716,6 +734,11 @@ static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
                             XIVE_ROUTER(spapr->xive), errp);
 }
 
+static void spapr_irq_post_load_xive(sPAPRMachineState *spapr)
+{
+    ;
+}
+
 /*
  * XIVE IRQ number space
  *
@@ -765,6 +788,7 @@ sPAPRIrq spapr_irq_xive = {
     .print_info  = spapr_irq_print_info_xive,
     .dt_populate = spapr_irq_dt_populate_xive,
     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
+    .post_load   = spapr_irq_post_load_xive,
 };
 
 /*
-- 
2.13.6