[Qemu-devel] [PATCH v4 07/28] ppc/xive: introduce the XiveRouter model

["Cédric Le Goater" <clg@kaod.org>]

The XiveRouter models the second sub-engine of the overall XIVE
architecture : the Interrupt Virtualization Routing Engine (IVRE).

The IVRE handles event notifications of the IVSE through MMIO stores
and performs the interrupt routing process. For this purpose, it uses
a set of table stored in system memory, the first of which being the
Interrupt Virtualization entries (IVE) table.

The IVT associates an interrupt source number with an Event Queue
Descriptor which will be used in a second phase of the routing process
to identify a notification target.

The XiveRouter is an abstract class which needs to be inherited from to
define a storage for the IVT, and other upcoming tables.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/xive.h      | 32 ++++++++++++++++++
 include/hw/ppc/xive_regs.h | 30 +++++++++++++++++
 hw/intc/xive.c             | 84 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 146 insertions(+)
 create mode 100644 include/hw/ppc/xive_regs.h

diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index be93fae6317b..13c414bf7d55 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -11,6 +11,7 @@
 #define PPC_XIVE_H
 
 #include "hw/sysbus.h"
+#include "hw/ppc/xive_regs.h"
 
 /*
  * XIVE Fabric (Interface between Source and Router)
@@ -168,4 +169,35 @@ static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
     }
 }
 
+/*
+ * XIVE Router
+ */
+
+typedef struct XiveRouter {
+    SysBusDevice    parent;
+
+    uint32_t        chip_id;
+} XiveRouter;
+
+#define TYPE_XIVE_ROUTER "xive-router"
+#define XIVE_ROUTER(obj)                                \
+    OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER)
+#define XIVE_ROUTER_CLASS(klass)                                        \
+    OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER)
+#define XIVE_ROUTER_GET_CLASS(obj)                              \
+    OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER)
+
+typedef struct XiveRouterClass {
+    SysBusDeviceClass parent;
+
+    /* XIVE table accessors */
+    int (*get_ive)(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive);
+    int (*set_ive)(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive);
+} XiveRouterClass;
+
+void xive_router_print_ive(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive,
+                           Monitor *mon);
+int xive_router_get_ive(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive);
+int xive_router_set_ive(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive);
+
 #endif /* PPC_XIVE_H */
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
new file mode 100644
index 000000000000..74420030111a
--- /dev/null
+++ b/include/hw/ppc/xive_regs.h
@@ -0,0 +1,30 @@
+/*
+ * QEMU PowerPC XIVE interrupt controller model
+ *
+ * Copyright (c) 2016-2018, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef _PPC_XIVE_REGS_H
+#define _PPC_XIVE_REGS_H
+
+/* IVE (Interrupt Virtualization Entry)
+ *
+ * One per interrupt source. Targets that interrupt to a given EQ
+ * and provides the corresponding logical interrupt number (EQ data)
+ */
+typedef struct XiveIVE {
+        /* Use a single 64-bit definition to make it easier to
+         * perform atomic updates
+         */
+        uint64_t        w;
+#define IVE_VALID       PPC_BIT(0)
+#define IVE_EQ_BLOCK    PPC_BITMASK(4, 7)        /* Destination EQ block# */
+#define IVE_EQ_INDEX    PPC_BITMASK(8, 31)       /* Destination EQ index */
+#define IVE_MASKED      PPC_BIT(32)              /* Masked */
+#define IVE_EQ_DATA     PPC_BITMASK(33, 63)      /* Data written to the EQ */
+} XiveIVE;
+
+#endif /* _PPC_XIVE_REGS_H */
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3f6fcb358f83..7f007d5a3ec0 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -443,6 +443,89 @@ static const TypeInfo xive_source_info = {
 };
 
 /*
+ * XIVE Router (aka. Virtualization Controller or IVRE)
+ */
+
+int xive_router_get_ive(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive)
+{
+    XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+    return xrc->get_ive(xrtr, lisn, ive);
+}
+
+int xive_router_set_ive(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive)
+{
+    XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+    return xrc->set_ive(xrtr, lisn, ive);
+}
+
+static void xive_router_notify(XiveFabric *xf, uint32_t lisn)
+{
+    XiveRouter *xrtr = XIVE_ROUTER(xf);
+    XiveIVE ive;
+
+    /* IVE cache lookup */
+    if (xive_router_get_ive(xrtr, lisn, &ive)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn);
+        return;
+    }
+
+    /* The IVRE has also a State Bit Cache for its internal sources
+     * which is also involed at this point. We can skip the SBC lookup
+     * here because the internal sources are modeled in a different
+     * way in QEMU.
+     */
+
+    if (!(ive.w & IVE_VALID)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn);
+        return;
+    }
+
+    if (ive.w & IVE_MASKED) {
+        /* Notification completed */
+        return;
+    }
+}
+
+static Property xive_router_properties[] = {
+    DEFINE_PROP_UINT32("chip-id", XiveRouter, chip_id, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xive_router_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    XiveFabricClass *xfc = XIVE_FABRIC_CLASS(klass);
+
+    dc->desc    = "XIVE Router Engine";
+    dc->props   = xive_router_properties;
+    xfc->notify = xive_router_notify;
+}
+
+static const TypeInfo xive_router_info = {
+    .name          = TYPE_XIVE_ROUTER,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .abstract      = true,
+    .class_size    = sizeof(XiveRouterClass),
+    .class_init    = xive_router_class_init,
+    .interfaces    = (InterfaceInfo[]) {
+        { TYPE_XIVE_FABRIC },
+        { }
+    }
+};
+
+void xive_router_print_ive(XiveRouter *xrtr, uint32_t lisn, XiveIVE *ive,
+                           Monitor *mon)
+{
+    if (!(ive->w & IVE_VALID)) {
+        return;
+    }
+
+    monitor_printf(mon, "  %8x %s\n", lisn, ive->w & IVE_MASKED ? "M" : " ");
+}
+
+/*
  * XIVE Fabric
  */
 static const TypeInfo xive_fabric_info = {
@@ -455,6 +538,7 @@ static void xive_register_types(void)
 {
     type_register_static(&xive_source_info);
     type_register_static(&xive_fabric_info);
+    type_register_static(&xive_router_info);
 }
 
 type_init(xive_register_types)
-- 
2.13.6