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From: David Gibson <david@gibson.dropbear.id.au>
To: Greg Kurz <groug@kaod.org>
Cc: luporl <leandro.lupori@gmail.com>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v3] target/ppc: Allow PIR read in privileged mode
Date: Fri, 8 Jun 2018 19:20:23 +1000	[thread overview]
Message-ID: <20180608092023.GU3344@umbus.fritz.box> (raw)
In-Reply-To: <20180606111922.66882650@bahia.lan>

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On Wed, Jun 06, 2018 at 11:19:22AM +0200, Greg Kurz wrote:
> On Wed, 6 Jun 2018 10:53:17 +1000
> David Gibson <david@gibson.dropbear.id.au> wrote:
> 
> > On Tue, Jun 05, 2018 at 06:46:12PM +0200, Greg Kurz wrote:
> > > On Mon, 4 Jun 2018 10:53:22 +1000
> > > David Gibson <david@gibson.dropbear.id.au> wrote:
> > >   
> > > > On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote:  
> > > > > According to PowerISA, the PIR register should be readable in privileged
> > > > > mode also, not only in hypervisor privileged mode.
> > > > > 
> > > > > PowerISA 3.0 - 4.3.3 Processor Identification Register
> > > > > 
> > > > > "Read access to the PIR is privileged; write access is not
> > > > > provided."    
> > > > 
> > > > Yes... but a little further down it says "The PIR is a hypervisor
> > > > resource".  Looking at the older 2.07 ISA, it says that
> > > > guest-supervisor mode reads to the PIR should be redirected to the
> > > > GPIR register, which this change won't accomplish.
> > > >   
> > > 
> > > Hmmm, there are two definitions for the PIR, one in Book III-S (4.3.3)
> > > and one in Book III-E (5.3.3). It looks like you're referring to the
> > > latter...
> > > 
> > > [Category:Embedded.Hypervisor]
> > > Read accesses to the PIR in guest supervisor state are
> > > mapped to the GPIR.
> > > 
> > > The Book III-S definition doesn't mention the GPIR.  
> > 
> > Oops, sorry.  Yes the GPIR stuff is only for BookE.  The statement
> > about the PIR being a hypervisor resource is definitely in the BookS
> > section, however (both 2.07 and 3.0).
> > 
> 
> Yes it is, but IIUC, this means that the guest cannot modify it, eg,
> do mtspr. Section 4.4.4 in Book III-S has a list of SPRs that seem to
> indicate that mfspr doesn't require hypervisor state with the PIR.

Ah, yes, I was looking for a summary that covered that, but hadn't
found it yet.

The patch doesn't actually apply clean to the current tree any more,
due to a rename.  So can you repost, and I'll apply.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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      reply	other threads:[~2018-06-08  9:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-07 13:48 [Qemu-devel] [PATCH] Allow PIR read in privileged mode luporl
2018-05-07 16:08 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2018-05-07 16:52   ` [Qemu-devel] [PATCH v3] target/ppc: " luporl
2018-06-04  0:53     ` David Gibson
2018-06-05 16:46       ` Greg Kurz
2018-06-06  0:53         ` David Gibson
2018-06-06  9:19           ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2018-06-08  9:20             ` David Gibson [this message]

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