* [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache @ 2018-06-12 5:16 Suraj Jitindar Singh 2018-06-12 5:16 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default Suraj Jitindar Singh 2018-06-12 11:19 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache David Gibson 0 siblings, 2 replies; 4+ messages in thread From: Suraj Jitindar Singh @ 2018-06-12 5:16 UTC (permalink / raw) To: qemu-ppc; +Cc: qemu-devel, david, groug, muriloo, sjitindarsingh For cap_ppc_safe_cache to be set to workaround, we require both a l1d cache flush instruction and private l1d cache. On POWER8 don't require private l1d cache. This means a guest on a POWER8 machine can make use of the cache flush workarounds. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> --- V1 -> V2: - Use mfpvr() to detect host type --- target/ppc/kvm.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 2c0c34e125..7fe9d0126b 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2412,11 +2412,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void) return cap_mmu_hash_v3; } +static bool kvmppc_power8_host(void) +{ + bool ret = false; +#ifdef TARGET_PPC64 + { + uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); + ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || + (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || + (base_pvr == CPU_POWERPC_POWER8_BASE); + } +#endif /* TARGET_PPC64 */ + return ret; +} + static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) { + bool l1d_thread_priv_req = !kvmppc_power8_host(); + if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { return 2; - } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && + } else if ((!l1d_thread_priv_req || + c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && (c.character & c.character_mask & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { return 1; -- 2.13.6 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default 2018-06-12 5:16 [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache Suraj Jitindar Singh @ 2018-06-12 5:16 ` Suraj Jitindar Singh 2018-06-12 11:19 ` David Gibson 2018-06-12 11:19 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache David Gibson 1 sibling, 1 reply; 4+ messages in thread From: Suraj Jitindar Singh @ 2018-06-12 5:16 UTC (permalink / raw) To: qemu-ppc; +Cc: qemu-devel, david, groug, muriloo, sjitindarsingh In default_caps_with_cpu() we set spapr_cap_cfpc to broken for POWER8 processors and before. Since we no longer require private l1d cache on POWER8 for this cap to be set to workaround change this to default to broken for POWER7 processors and before. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> --- V1 -> V2: - No Change --- hw/ppc/spapr_caps.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 531e145114..00e43a9ba7 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -335,14 +335,10 @@ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr, caps = smc->default_caps; - if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, - 0, spapr->max_compat_pvr)) { - caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; - } - if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, spapr->max_compat_pvr)) { caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; + caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; } if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06_PLUS, -- 2.13.6 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default 2018-06-12 5:16 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default Suraj Jitindar Singh @ 2018-06-12 11:19 ` David Gibson 0 siblings, 0 replies; 4+ messages in thread From: David Gibson @ 2018-06-12 11:19 UTC (permalink / raw) To: Suraj Jitindar Singh; +Cc: qemu-ppc, qemu-devel, groug, muriloo [-- Attachment #1: Type: text/plain, Size: 1651 bytes --] On Tue, Jun 12, 2018 at 03:16:30PM +1000, Suraj Jitindar Singh wrote: > In default_caps_with_cpu() we set spapr_cap_cfpc to broken for POWER8 > processors and before. > > Since we no longer require private l1d cache on POWER8 for this cap to > be set to workaround change this to default to broken for POWER7 > processors and before. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> > Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Applied to ppc-for-3.0, thanks. > > --- > > V1 -> V2: > - No Change > > --- > hw/ppc/spapr_caps.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c > index 531e145114..00e43a9ba7 100644 > --- a/hw/ppc/spapr_caps.c > +++ b/hw/ppc/spapr_caps.c > @@ -335,14 +335,10 @@ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr, > > caps = smc->default_caps; > > - if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, > - 0, spapr->max_compat_pvr)) { > - caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; > - } > - > if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, > 0, spapr->max_compat_pvr)) { > caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; > + caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; > } > > if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06_PLUS, -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache 2018-06-12 5:16 [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache Suraj Jitindar Singh 2018-06-12 5:16 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default Suraj Jitindar Singh @ 2018-06-12 11:19 ` David Gibson 1 sibling, 0 replies; 4+ messages in thread From: David Gibson @ 2018-06-12 11:19 UTC (permalink / raw) To: Suraj Jitindar Singh; +Cc: qemu-ppc, qemu-devel, groug, muriloo [-- Attachment #1: Type: text/plain, Size: 2094 bytes --] On Tue, Jun 12, 2018 at 03:16:29PM +1000, Suraj Jitindar Singh wrote: > For cap_ppc_safe_cache to be set to workaround, we require both a l1d > cache flush instruction and private l1d cache. > > On POWER8 don't require private l1d cache. This means a guest on a > POWER8 machine can make use of the cache flush workarounds. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Applied to ppc-for-3.0, thanks. > > --- > > V1 -> V2: > - Use mfpvr() to detect host type > > --- > target/ppc/kvm.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c > index 2c0c34e125..7fe9d0126b 100644 > --- a/target/ppc/kvm.c > +++ b/target/ppc/kvm.c > @@ -2412,11 +2412,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void) > return cap_mmu_hash_v3; > } > > +static bool kvmppc_power8_host(void) > +{ > + bool ret = false; > +#ifdef TARGET_PPC64 > + { > + uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); > + ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || > + (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || > + (base_pvr == CPU_POWERPC_POWER8_BASE); > + } > +#endif /* TARGET_PPC64 */ > + return ret; > +} > + > static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) > { > + bool l1d_thread_priv_req = !kvmppc_power8_host(); > + > if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { > return 2; > - } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && > + } else if ((!l1d_thread_priv_req || > + c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && > (c.character & c.character_mask > & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { > return 1; -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-06-12 11:45 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-06-12 5:16 [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache Suraj Jitindar Singh 2018-06-12 5:16 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default Suraj Jitindar Singh 2018-06-12 11:19 ` David Gibson 2018-06-12 11:19 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache David Gibson
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