From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
richard.henderson@linaro.org,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [RISU PATCH v3 17/22] risu_reginfo: introduce reginfo_size()
Date: Wed, 13 Jun 2018 13:55:56 +0100 [thread overview]
Message-ID: <20180613125601.14371-18-alex.bennee@linaro.org> (raw)
In-Reply-To: <20180613125601.14371-1-alex.bennee@linaro.org>
In preparation for conditionally supporting SVE we need to be able to
have different sized reginfos. This introduces reginfo_size() to
abstract the size away to the code the actually knows. For aarch64 we
also use this while initialising the block.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
reginfo.c | 6 +++---
risu.h | 3 +++
risu_reginfo_aarch64.c | 11 ++++++++++-
risu_reginfo_aarch64.h | 1 +
risu_reginfo_arm.c | 5 +++++
risu_reginfo_m68k.c | 5 +++++
risu_reginfo_ppc64.c | 5 +++++
7 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/reginfo.c b/reginfo.c
index 1f55d06..dd42ae2 100644
--- a/reginfo.c
+++ b/reginfo.c
@@ -39,7 +39,7 @@ int send_register_info(write_fn write_fn, void *uc)
switch (op) {
case OP_TESTEND:
- write_fn(&ri, sizeof(ri));
+ write_fn(&ri, reginfo_size());
/* if we are tracing write_fn will return 0 unlike a remote
end, hence we force return of 1 here */
return 1;
@@ -58,7 +58,7 @@ int send_register_info(write_fn write_fn, void *uc)
/* Do a simple register compare on (a) explicit request
* (b) end of test (c) a non-risuop UNDEF
*/
- return write_fn(&ri, sizeof(ri));
+ return write_fn(&ri, reginfo_size());
}
return 0;
}
@@ -101,7 +101,7 @@ int recv_and_compare_register_info(read_fn read_fn,
/* Do a simple register compare on (a) explicit request
* (b) end of test (c) a non-risuop UNDEF
*/
- if (read_fn(&apprentice_ri, sizeof(apprentice_ri))) {
+ if (read_fn(&apprentice_ri, reginfo_size())) {
packet_mismatch = 1;
resp = 2;
} else if (!reginfo_is_eq(&master_ri, &apprentice_ri)) {
diff --git a/risu.h b/risu.h
index 48c50d9..8d2d646 100644
--- a/risu.h
+++ b/risu.h
@@ -133,4 +133,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f);
/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f);
+/* return size of reginfo */
+const int reginfo_size(void);
+
#endif /* RISU_H */
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 62a5599..5da9e39 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -15,6 +15,8 @@
#include <string.h>
#include <signal.h> /* for FPSIMD_MAGIC */
#include <stdlib.h>
+#include <stddef.h>
+#include <assert.h>
#include "risu.h"
#include "risu_reginfo_aarch64.h"
@@ -27,6 +29,13 @@ void process_arch_opt(int opt, const char *arg)
abort();
}
+const int reginfo_size(void)
+{
+ const int size = offsetof(struct reginfo, simd.end);
+ assert(sizeof(struct reginfo)==size);
+ return size;
+}
+
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc)
{
@@ -71,7 +80,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc)
/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
{
- return memcmp(r1, r2, sizeof(*r1)) == 0;
+ return memcmp(r1, r2, reginfo_size()) == 0;
}
/* reginfo_dump: print state to a stream, returns nonzero on success */
diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h
index a1c708b..ef97622 100644
--- a/risu_reginfo_aarch64.h
+++ b/risu_reginfo_aarch64.h
@@ -15,6 +15,7 @@
struct simd_reginfo {
__uint128_t vregs[32];
+ char end[0];
};
struct reginfo {
diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c
index 12ad0ef..3662f12 100644
--- a/risu_reginfo_arm.c
+++ b/risu_reginfo_arm.c
@@ -36,6 +36,11 @@ void process_arch_opt(int opt, const char *arg)
abort();
}
+const int reginfo_size(void)
+{
+ return sizeof(struct reginfo);
+}
+
static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc)
{
/* Read VFP registers. These live in uc->uc_regspace, which is
diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c
index 7a1c5a9..32b28c8 100644
--- a/risu_reginfo_m68k.c
+++ b/risu_reginfo_m68k.c
@@ -23,6 +23,11 @@ void process_arch_opt(int opt, const char *arg)
abort();
}
+const int reginfo_size(void)
+{
+ return sizeof(struct reginfo);
+}
+
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc)
{
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index 4b70460..f9d2f0d 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -31,6 +31,11 @@ void process_arch_opt(int opt, const char *arg)
abort();
}
+const int reginfo_size(void)
+{
+ return sizeof(struct reginfo);
+}
+
/* reginfo_init: initialize with a ucontext */
void reginfo_init(struct reginfo *ri, ucontext_t *uc)
{
--
2.17.1
next prev parent reply other threads:[~2018-06-13 12:56 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-13 12:55 [Qemu-devel] [RISU PATCH v3 00/22] SVE support and various misc fixes Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 01/22] risu_reginfo_aarch64: include signal.h for FPSIMD_MAGIC Alex Bennée
2018-06-14 5:40 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 02/22] comms: include header for writev Alex Bennée
2018-06-14 5:41 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 03/22] build-all-arches: expand the range of docker images Alex Bennée
2018-06-14 5:42 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 04/22] build-all-arches: do a distclean $(SRC) configured Alex Bennée
2018-06-14 5:43 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 05/22] risu: add zlib indication to help text Alex Bennée
2018-06-14 5:47 ` Richard Henderson
2018-06-14 8:34 ` Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 06/22] Makefile: include risu_reginfo_$(ARCH) in HDRS Alex Bennée
2018-06-14 5:50 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 07/22] risugen: add --sve support Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 08/22] risugen: Initialize sve predicates with random data Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 09/22] risugen: use fewer insns for aarch64 immediate load Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 10/22] risugen: add reg_plus_imm_pl and reg_plus_imm_vl address helpers Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 11/22] risugen: add dtype_msz address helper Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 12/22] contrib/generate_all.sh: allow passing of arguments to risugen Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 13/22] risu: move optional args to each architecture Alex Bennée
2018-06-14 20:20 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 14/22] risu: add process_arch_opt Alex Bennée
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 15/22] risu_reginfo_aarch64: drop stray ; Alex Bennée
2018-06-14 20:23 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 16/22] risu_reginfo_aarch64: unionify VFP regs Alex Bennée
2018-06-14 20:24 ` Richard Henderson
2018-06-13 12:55 ` Alex Bennée [this message]
2018-06-14 20:25 ` [Qemu-devel] [RISU PATCH v3 17/22] risu_reginfo: introduce reginfo_size() Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 18/22] risu_reginfo_aarch64: left justify regnums and drop masks Alex Bennée
2018-06-14 20:26 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 19/22] risu_reginfo_aarch64: add support for copying SVE register state Alex Bennée
2018-06-14 20:33 ` Richard Henderson
2018-06-13 12:55 ` [Qemu-devel] [RISU PATCH v3 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch Alex Bennée
2018-06-14 20:42 ` Richard Henderson
2018-06-13 12:56 ` [Qemu-devel] [RISU PATCH v3 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture Alex Bennée
2018-06-13 12:56 ` [Qemu-devel] [RISU PATCH v3 22/22] risu_reginfo_aarch64: handle variable VQ Alex Bennée
2018-06-14 20:50 ` Richard Henderson
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