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From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: pbonzini@redhat.com, rth@twiddle.net,
	Eduardo Habkost <ehabkost@redhat.com>,
	kvm@vger.kernel.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit
Date: Wed, 13 Jun 2018 17:21:29 +0100	[thread overview]
Message-ID: <20180613162129.GI19901@redhat.com> (raw)
In-Reply-To: <20180613160959.GF11438@char.us.oracle.com>

On Wed, Jun 13, 2018 at 12:09:59PM -0400, Konrad Rzeszutek Wilk wrote:
> On Wed, Jun 13, 2018 at 11:19:49AM +0100, Daniel P. Berrangé wrote:
> > On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote:
> > > On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote:
> > > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote:
> > > > > AMD future CPUs expose _two_ ways to utilize the Intel equivalant
> > > > > of the Speculative Store Bypass Disable. The first is via
> > > > > the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
> > > > > is via the SPEC_CTRL MSR (0x48). The document titled:
> > > > > 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> > > > > 
> > > > > gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
> > > > > 
> > > > > A copy of this document is available at
> > > > >       https://bugzilla.kernel.org/show_bug.cgi?id=199889
> > > > > 
> > > > > Anyhow, this means that on future AMD CPUs there will be  _two_ ways to
> > > > > deal with SSBD.
> > > > 
> > > > Does anybody know if there are AMD CPUs where virt-ssbd won't
> > > > work and would require amd-ssbd to mitigate vulnerabilities?
> > > > 
> > > > Also, do we have kernel arch/x86/kvm/cpuid.c patches, already?
> > > 
> > > Not yet. They are being discussed right now. I figured I would send
> > > these patches out as a 'Hey, coming at you!', but failed to change
> > > the title to be 'RFC'.
> > > 
> > > > I prefer to add new CPUID flag names only after the flag name is
> > > > already agreed upon on the kernel side.
> > > 
> > > Of course. I will respin once that discussion has calmed down.
> > 
> > Looks like the kernel side has merged now, and we'll need to rename
> > the 2nd CPU bit from what I see.
> 
> What name did you have in mind?

IIUC from the kernel patches, it will be reported as 'amd-ssbd' and
'amd-ssb-no' in /proc/cpuinfo, so only your second patch needs a simple
tweak to match that naming.

Regards,
Daniel
-- 
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  reply	other threads:[~2018-06-13 16:21 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20180601145921.9500-1-konrad.wilk@oracle.com>
2018-06-01 15:38 ` [Qemu-devel] [PATCH QEMU] Patches for new AMD CPU bits Konrad Rzeszutek Wilk
2018-06-01 15:38   ` [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit Konrad Rzeszutek Wilk
2018-06-04  8:54     ` Daniel P. Berrangé
2018-06-04 20:20       ` Konrad Rzeszutek Wilk
2018-06-04 20:07     ` Eduardo Habkost
2018-06-04 20:22       ` Konrad Rzeszutek Wilk
2018-06-04 21:15         ` Eduardo Habkost
2018-06-05 21:40           ` Konrad Rzeszutek Wilk
2018-06-13 10:19         ` Daniel P. Berrangé
2018-06-13 16:09           ` Konrad Rzeszutek Wilk
2018-06-13 16:21             ` Daniel P. Berrangé [this message]
2018-06-13 16:34               ` Konrad Rzeszutek Wilk
2018-06-13 16:39                 ` Daniel P. Berrangé
2018-06-13 16:56                   ` Eduardo Habkost
2018-06-05 13:31       ` Tom Lendacky
2018-06-05 14:04         ` Daniel P. Berrangé
2018-06-06 14:20         ` Daniel P. Berrangé
2018-06-08 21:22           ` Tom Lendacky
2018-06-01 15:38   ` [Qemu-devel] [PATCH 2/2] i386: Define AMD's no SSB mitigation needed Konrad Rzeszutek Wilk
2018-06-13 21:38   ` [Qemu-devel] [PATCH QEMU] Patches for new AMD CPU bits Eduardo Habkost

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