[Qemu-devel] [PATCH v1 0/2] target-microblaze: Coverity fixes

[Qemu-devel] [PATCH v1 0/2] target-microblaze: Coverity fixes

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

This series has fixes for the Coverity issues that Peter Maydell
reported.

CID 1391441
CID 1391443

Best regards,
Edgar


Edgar E. Iglesias (2):
  target-microblaze: mmu: Correct masking of output addresses
  target-microblaze: Rework NOP/zero instruction handling

 target/microblaze/mmu.c       |  1 -
 target/microblaze/translate.c | 15 ++++-----------
 2 files changed, 4 insertions(+), 12 deletions(-)

-- 
2.14.1

[Qemu-devel] [PATCH v1 1/2] target-microblaze: mmu: Correct masking of output addresses

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Correct the masking of output addresses.

This fixes Coverity CID 1391441.

Fixes: commit 3924a9aa02
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/mmu.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index f4ceaea520..fcf86b12d5 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -159,7 +159,6 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
 
             lu->vaddr = tlb_tag;
             lu->paddr = tlb_rpn & mmu->c_addr_mask;
-            lu->paddr = tlb_rpn;
             lu->size = tlb_size;
             lu->err = ERR_HIT;
             lu->idx = i;
-- 
2.14.1

Re: [Qemu-devel] [PATCH v1 1/2] target-microblaze: mmu: Correct masking of output addresses

[Alistair Francis]

On Thu, Jun 14, 2018 at 1:25 PM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Correct the masking of output addresses.
>
> This fixes Coverity CID 1391441.
>
> Fixes: commit 3924a9aa02
> Reported-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/microblaze/mmu.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index f4ceaea520..fcf86b12d5 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -159,7 +159,6 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
>
>              lu->vaddr = tlb_tag;
>              lu->paddr = tlb_rpn & mmu->c_addr_mask;
> -            lu->paddr = tlb_rpn;
>              lu->size = tlb_size;
>              lu->err = ERR_HIT;
>              lu->idx = i;
> --
> 2.14.1
>
>

Re: [Qemu-devel] [PATCH v1 1/2] target-microblaze: mmu: Correct masking of output addresses

[Philippe Mathieu-Daudé]

On 06/14/2018 05:25 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Correct the masking of output addresses.
> 
> This fixes Coverity CID 1391441.
> 
> Fixes: commit 3924a9aa02
> Reported-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/microblaze/mmu.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index f4ceaea520..fcf86b12d5 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -159,7 +159,6 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
>  
>              lu->vaddr = tlb_tag;
>              lu->paddr = tlb_rpn & mmu->c_addr_mask;
> -            lu->paddr = tlb_rpn;
>              lu->size = tlb_size;
>              lu->err = ERR_HIT;
>              lu->idx = i;
> 

[Qemu-devel] [PATCH v1 2/2] target-microblaze: Rework NOP/zero instruction handling

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Remove the abort on a sequence of NOP/zero instructions.
Always return early and avoid decoding NOP/zero instructions.

This fixes Coverity CID 1391443.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 6c64946398..78ca265b04 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -90,7 +90,6 @@ typedef struct DisasContext {
     uint32_t jmp_pc;
 
     int abort_at_next_insn;
-    int nr_nops;
     struct TranslationBlock *tb;
     int singlestep_enabled;
 } DisasContext;
@@ -1576,17 +1575,12 @@ static inline void decode(DisasContext *dc, uint32_t ir)
     dc->ir = ir;
     LOG_DIS("%8.8x\t", dc->ir);
 
-    if (dc->ir)
-        dc->nr_nops = 0;
-    else {
+    if (ir == 0) {
         trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
-
-        LOG_DIS("nr_nops=%d\t", dc->nr_nops);
-        dc->nr_nops++;
-        if (dc->nr_nops > 4) {
-            cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");
-        }
+        /* Don't decode nop/zero instructions any further.  */
+        return;
     }
+
     /* bit 2 seems to indicate insn type.  */
     dc->type_b = ir & (1 << 29);
 
@@ -1633,7 +1627,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
     dc->singlestep_enabled = cs->singlestep_enabled;
     dc->cpustate_changed = 0;
     dc->abort_at_next_insn = 0;
-    dc->nr_nops = 0;
 
     if (pc_start & 3) {
         cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
-- 
2.14.1

Re: [Qemu-devel] [PATCH v1 2/2] target-microblaze: Rework NOP/zero instruction handling

[Philippe Mathieu-Daudé]

On 06/14/2018 05:25 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Remove the abort on a sequence of NOP/zero instructions.
> Always return early and avoid decoding NOP/zero instructions.
> 
> This fixes Coverity CID 1391443.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/microblaze/translate.c | 15 ++++-----------
>  1 file changed, 4 insertions(+), 11 deletions(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 6c64946398..78ca265b04 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -90,7 +90,6 @@ typedef struct DisasContext {
>      uint32_t jmp_pc;
>  
>      int abort_at_next_insn;
> -    int nr_nops;
>      struct TranslationBlock *tb;
>      int singlestep_enabled;
>  } DisasContext;
> @@ -1576,17 +1575,12 @@ static inline void decode(DisasContext *dc, uint32_t ir)
>      dc->ir = ir;
>      LOG_DIS("%8.8x\t", dc->ir);
>  
> -    if (dc->ir)
> -        dc->nr_nops = 0;
> -    else {
> +    if (ir == 0) {
>          trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
> -
> -        LOG_DIS("nr_nops=%d\t", dc->nr_nops);
> -        dc->nr_nops++;
> -        if (dc->nr_nops > 4) {
> -            cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");
> -        }
> +        /* Don't decode nop/zero instructions any further.  */
> +        return;
>      }
> +
>      /* bit 2 seems to indicate insn type.  */
>      dc->type_b = ir & (1 << 29);
>  
> @@ -1633,7 +1627,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
>      dc->singlestep_enabled = cs->singlestep_enabled;
>      dc->cpustate_changed = 0;
>      dc->abort_at_next_insn = 0;
> -    dc->nr_nops = 0;
>  
>      if (pc_start & 3) {
>          cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
>