From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57417) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUz5b-0003Xx-8p for qemu-devel@nongnu.org; Mon, 18 Jun 2018 14:41:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fUz5a-0004ue-EW for qemu-devel@nongnu.org; Mon, 18 Jun 2018 14:41:19 -0400 Received: from mail-pg0-x22f.google.com ([2607:f8b0:400e:c05::22f]:34482) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fUz5a-0004th-8M for qemu-devel@nongnu.org; Mon, 18 Jun 2018 14:41:18 -0400 Received: by mail-pg0-x22f.google.com with SMTP id q4-v6so7935204pgr.1 for ; Mon, 18 Jun 2018 11:41:18 -0700 (PDT) From: Richard Henderson Date: Mon, 18 Jun 2018 08:40:39 -1000 Message-Id: <20180618184046.6270-16-richard.henderson@linaro.org> In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org> References: <20180618184046.6270-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 15/22] target/openrisc: Stub out handle_mmu_fault for softmmu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: shorne@gmail.com This hook is only used by CONFIG_USER_ONLY. Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 35 +++++------------------------------ 1 file changed, 5 insertions(+), 30 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index a4613e9ae4..f4c0a3e217 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -177,42 +177,17 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, cpu->env.lock_addr = -1; } -#ifndef CONFIG_USER_ONLY int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { +#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret = 0; - hwaddr physical = 0; - int prot = 0; - - ret = get_phys_addr(cpu, &physical, &prot, address, rw); - - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) { - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret = 1; - } - - return ret; -} + cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + return 1; #else -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret = 0; - - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret = 1; - - return ret; -} + g_assert_not_reached(); #endif +} #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -- 2.17.1