From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: shorne@gmail.com
Subject: [Qemu-devel] [PATCH v2 17/22] target/openrisc: Increase the TLB size
Date: Mon, 18 Jun 2018 08:40:41 -1000 [thread overview]
Message-ID: <20180618184046.6270-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org>
The architecture supports 128 TLB entries. There is no reason
not to provide all of them. In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2:
- Change VMState version.
---
target/openrisc/cpu.h | 2 +-
target/openrisc/cpu.c | 6 ++++--
target/openrisc/machine.c | 5 ++---
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 53abe965e8..8035654087 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -222,7 +222,7 @@ enum {
/* TLB size */
enum {
- TLB_SIZE = 64,
+ TLB_SIZE = 128,
TLB_MASK = TLB_SIZE - 1,
};
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 4c166c6329..677f02efa4 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -52,8 +52,10 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
UPR_PMP;
- cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
- cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
+ cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
+ | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
+ cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
+ | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x00000000;
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 3fc837b925..1eedbf3dbe 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = {
static const VMStateDescription vmstate_cpu_tlb = {
.name = "cpu_tlb",
- .version_id = 1,
- .minimum_version_id = 1,
- .minimum_version_id_old = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
--
2.17.1
next prev parent reply other threads:[~2018-06-18 18:41 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-18 18:40 [Qemu-devel] [PATCH v2 00/22] target/openrisc improvements Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 01/22] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 02/22] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 03/22] target/openrisc: Fix singlestep_enabled Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 04/22] target/openrisc: Link more translation blocks Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 05/22] target/openrisc: Split out is_user Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 06/22] target/openrisc: Exit the TB after l.mtspr Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 07/22] target/openrisc: Form the spr index from tcg Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 08/22] target/openrisc: Merge tlb allocation into CPUOpenRISCState Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 09/22] target/openrisc: Remove indirect function calls for mmu Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 10/22] target/openrisc: Merge mmu_helper.c into mmu.c Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 11/22] target/openrisc: Reduce tlb to a single dimension Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 12/22] target/openrisc: Fix tlb flushing in mtspr Richard Henderson
2018-06-22 6:40 ` Stafford Horne
2018-06-24 3:10 ` Stafford Horne
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index Richard Henderson
2018-06-24 3:44 ` Stafford Horne
2018-06-26 22:07 ` Stafford Horne
2018-06-26 22:26 ` Richard Henderson
2018-06-27 12:59 ` Stafford Horne
2018-06-27 13:50 ` Richard Henderson
2018-06-27 23:08 ` Stafford Horne
2018-06-28 1:36 ` Richard Henderson
2018-06-28 21:27 ` Stafford Horne
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 14/22] target/openrisc: Use identical sizes for ITLB and DTLB Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 15/22] target/openrisc: Stub out handle_mmu_fault for softmmu Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 16/22] target/openrisc: Log interrupts Richard Henderson
2018-06-18 18:40 ` Richard Henderson [this message]
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 18/22] target/openrisc: Reorg tlb lookup Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 19/22] target/openrisc: Add print_insn_or1k Richard Henderson
2018-06-27 16:03 ` Philippe Mathieu-Daudé
2018-06-27 16:15 ` Richard Henderson
2018-06-27 23:17 ` Stafford Horne
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 20/22] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Richard Henderson
2018-06-27 19:02 ` Laurent Vivier
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 21/22] linux-user: Implement signals for openrisc Richard Henderson
2018-06-27 19:43 ` Laurent Vivier
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 22/22] linux-user: Fix struct sigaltstack " Richard Henderson
2018-06-18 21:05 ` [Qemu-devel] [PATCH v2 00/22] target/openrisc improvements no-reply
2018-06-21 11:00 ` Stafford Horne
2018-06-21 11:25 ` Richard Henderson
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