qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: shorne@gmail.com
Subject: [Qemu-devel] [PATCH v2 05/22] target/openrisc: Split out is_user
Date: Mon, 18 Jun 2018 08:40:29 -1000	[thread overview]
Message-ID: <20180618184046.6270-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180618184046.6270-1-richard.henderson@linaro.org>

This allows us to limit the amount of ifdefs and isolate
the test for usermode.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/translate.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 422f22d7f8..16e69c75fa 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -54,6 +54,15 @@ typedef struct DisasContext {
     target_ulong jmp_pc_imm;
 } DisasContext;
 
+static inline bool is_user(DisasContext *dc)
+{
+#ifdef CONFIG_USER_ONLY
+    return true;
+#else
+    return dc->mem_idx == MMU_USER_IDX;
+#endif
+}
+
 /* Include the auto-generated decoder.  */
 #include "decode.inc.c"
 
@@ -914,17 +923,13 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
     LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k);
     check_r0_write(a->d);
 
-#ifdef CONFIG_USER_ONLY
-    gen_illegal_exception(dc);
-#else
-    if (dc->mem_idx == MMU_USER_IDX) {
+    if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
         TCGv_i32 ti = tcg_const_i32(a->k);
         gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
         tcg_temp_free_i32(ti);
     }
-#endif
     return true;
 }
 
@@ -932,17 +937,13 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
 {
     LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k);
 
-#ifdef CONFIG_USER_ONLY
-    gen_illegal_exception(dc);
-#else
-    if (dc->mem_idx == MMU_USER_IDX) {
+    if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
         TCGv_i32 ti = tcg_const_i32(a->k);
         gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
         tcg_temp_free_i32(ti);
     }
-#endif
     return true;
 }
 
@@ -1204,16 +1205,12 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
 {
     LOG_DIS("l.rfe\n");
 
-#ifdef CONFIG_USER_ONLY
-    gen_illegal_exception(dc);
-#else
-    if (dc->mem_idx == MMU_USER_IDX) {
+    if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
         gen_helper_rfe(cpu_env);
         dc->base.is_jmp = DISAS_EXIT;
     }
-#endif
     return true;
 }
 
-- 
2.17.1

  parent reply	other threads:[~2018-06-18 18:41 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-18 18:40 [Qemu-devel] [PATCH v2 00/22] target/openrisc improvements Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 01/22] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 02/22] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 03/22] target/openrisc: Fix singlestep_enabled Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 04/22] target/openrisc: Link more translation blocks Richard Henderson
2018-06-18 18:40 ` Richard Henderson [this message]
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 06/22] target/openrisc: Exit the TB after l.mtspr Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 07/22] target/openrisc: Form the spr index from tcg Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 08/22] target/openrisc: Merge tlb allocation into CPUOpenRISCState Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 09/22] target/openrisc: Remove indirect function calls for mmu Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 10/22] target/openrisc: Merge mmu_helper.c into mmu.c Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 11/22] target/openrisc: Reduce tlb to a single dimension Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 12/22] target/openrisc: Fix tlb flushing in mtspr Richard Henderson
2018-06-22  6:40   ` Stafford Horne
2018-06-24  3:10     ` Stafford Horne
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index Richard Henderson
2018-06-24  3:44   ` Stafford Horne
2018-06-26 22:07     ` Stafford Horne
2018-06-26 22:26       ` Richard Henderson
2018-06-27 12:59         ` Stafford Horne
2018-06-27 13:50           ` Richard Henderson
2018-06-27 23:08             ` Stafford Horne
2018-06-28  1:36               ` Richard Henderson
2018-06-28 21:27                 ` Stafford Horne
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 14/22] target/openrisc: Use identical sizes for ITLB and DTLB Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 15/22] target/openrisc: Stub out handle_mmu_fault for softmmu Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 16/22] target/openrisc: Log interrupts Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 17/22] target/openrisc: Increase the TLB size Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 18/22] target/openrisc: Reorg tlb lookup Richard Henderson
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 19/22] target/openrisc: Add print_insn_or1k Richard Henderson
2018-06-27 16:03   ` Philippe Mathieu-Daudé
2018-06-27 16:15     ` Richard Henderson
2018-06-27 23:17       ` Stafford Horne
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 20/22] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Richard Henderson
2018-06-27 19:02   ` Laurent Vivier
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 21/22] linux-user: Implement signals for openrisc Richard Henderson
2018-06-27 19:43   ` Laurent Vivier
2018-06-18 18:40 ` [Qemu-devel] [PATCH v2 22/22] linux-user: Fix struct sigaltstack " Richard Henderson
2018-06-18 21:05 ` [Qemu-devel] [PATCH v2 00/22] target/openrisc improvements no-reply
2018-06-21 11:00 ` Stafford Horne
2018-06-21 11:25   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180618184046.6270-6-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=shorne@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).