From: Yongbok Kim <yongbok.kim@mips.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Aleksandar.Markovic@mips.com,
James.Hogan@mips.com, Paul.Burton@mips.com,
Matthew.Fortune@mips.com, Stefan.Markovic@mips.com
Subject: [Qemu-devel] [PATCH 10/35] target/mips: Add nanoMIPS pool32f instructions
Date: Wed, 20 Jun 2018 13:05:55 +0100 [thread overview]
Message-ID: <20180620120620.12806-11-yongbok.kim@mips.com> (raw)
In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com>
Add nanoMIPS pool32f floating point instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
---
target/mips/translate.c | 300 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 300 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f3a8845..0175a57 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16313,6 +16313,305 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
+static void gen_pool32f_nanomips_insn(DisasContext *ctx)
+{
+ int rt, rs, rd;
+
+ rt = (ctx->opcode >> 21) & 0x1f;
+ rs = (ctx->opcode >> 16) & 0x1f;
+ rd = (ctx->opcode >> 11) & 0x1f;
+
+ if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
+ generate_exception_end(ctx, EXCP_RI);
+ return;
+ }
+ check_cp1_enabled(ctx);
+ switch (ctx->opcode & 0x07) {
+ case NM_POOL32F_0:
+ switch ((ctx->opcode >> 3) & 0x7f) {
+ case NM_RINT_S:
+ gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
+ break;
+ case NM_RINT_D:
+ gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
+ break;
+ case NM_CLASS_S:
+ gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
+ break;
+ case NM_CLASS_D:
+ gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
+ break;
+ case NM_ADD_S:
+ gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0);
+ break;
+ case NM_ADD_D:
+ gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0);
+ break;
+ case NM_SUB_S:
+ gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0);
+ break;
+ case NM_SUB_D:
+ gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0);
+ break;
+ case NM_MUL_S:
+ gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0);
+ break;
+ case NM_MUL_D:
+ gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0);
+ break;
+ case NM_DIV_S:
+ gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0);
+ break;
+ case NM_DIV_D:
+ gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0);
+ break;
+ case NM_SELEQZ_S:
+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+ break;
+ case NM_SELEQZ_D:
+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+ break;
+ case NM_SELNEZ_S:
+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+ break;
+ case NM_SELNEZ_D:
+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+ break;
+ case NM_SEL_S:
+ gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
+ break;
+ case NM_SEL_D:
+ gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
+ break;
+ case NM_MADDF_S:
+ gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0);
+ break;
+ case NM_MADDF_D:
+ gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0);
+ break;
+ case NM_MSUBF_S:
+ gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0);
+ break;
+ case NM_MSUBF_D:
+ gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_POOL32F_3:
+ switch ((ctx->opcode >> 3) & 0x07) {
+ case NM_MIN_FMT:
+ switch ((ctx->opcode >> 9) & 1) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_MAX_FMT:
+ switch ((ctx->opcode >> 9) & 1) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_MINA_FMT:
+ switch ((ctx->opcode >> 9) & 1) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_MAXA_FMT:
+ switch ((ctx->opcode >> 9) & 1) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
+ break;
+ }
+ break;
+ case NM_POOL32FXF:
+ switch ((ctx->opcode >> 6) & 0xff) {
+ case NM_CFC1:
+ gen_cp1(ctx, OPC_CFC1, rt, rs);
+ break;
+ case NM_CTC1:
+ gen_cp1(ctx, OPC_CTC1, rt, rs);
+ break;
+ case NM_MFC1:
+ gen_cp1(ctx, OPC_MFC1, rt, rs);
+ break;
+ case NM_MTC1:
+ gen_cp1(ctx, OPC_MTC1, rt, rs);
+ break;
+ case NM_MFHC1:
+ gen_cp1(ctx, OPC_MFHC1, rt, rs);
+ break;
+ case NM_MTHC1:
+ gen_cp1(ctx, OPC_MTHC1, rt, rs);
+ break;
+ case NM_CVT_S_PL:
+ gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_PU:
+ gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0);
+ break;
+ default:
+ switch ((ctx->opcode >> 6) & 0x1ff) {
+ case NM_CVT_L_S:
+ gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0);
+ break;
+ case NM_CVT_L_D:
+ gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0);
+ break;
+ case NM_CVT_W_S:
+ gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0);
+ break;
+ case NM_CVT_W_D:
+ gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0);
+ break;
+ case NM_RSQRT_S:
+ gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0);
+ break;
+ case NM_RSQRT_D:
+ gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0);
+ break;
+ case NM_SQRT_S:
+ gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0);
+ break;
+ case NM_SQRT_D:
+ gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0);
+ break;
+ case NM_RECIP_S:
+ gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0);
+ break;
+ case NM_RECIP_D:
+ gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_L_S:
+ gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_L_D:
+ gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_W_S:
+ gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0);
+ break;
+ case NM_FLOOR_W_D:
+ gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_L_S:
+ gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_L_D:
+ gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_W_S:
+ gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0);
+ break;
+ case NM_CEIL_W_D:
+ gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_L_S:
+ gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_L_D:
+ gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_W_S:
+ gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0);
+ break;
+ case NM_TRUNC_W_D:
+ gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_L_S:
+ gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_L_D:
+ gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_W_S:
+ gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0);
+ break;
+ case NM_ROUND_W_D:
+ gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0);
+ break;
+ case NM_MOV_S:
+ gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0);
+ break;
+ case NM_MOV_D:
+ gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0);
+ break;
+ case NM_ABS_S:
+ gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0);
+ break;
+ case NM_ABS_D:
+ gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0);
+ break;
+ case NM_NEG_S:
+ gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0);
+ break;
+ case NM_NEG_D:
+ gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0);
+ break;
+ case NM_CVT_D_S:
+ gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0);
+ break;
+ case NM_CVT_D_W:
+ gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0);
+ break;
+ case NM_CVT_D_L:
+ gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_D:
+ gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_W:
+ gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0);
+ break;
+ case NM_CVT_S_L:
+ gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case NM_POOL32F_5:
+ switch ((ctx->opcode >> 3) & 0x07) {
+ case NM_CMP_CONDN_S:
+ gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
+ break;
+ case NM_CMP_CONDN_D:
+ gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint16_t insn;
@@ -16612,6 +16911,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_POOL32F:
+ gen_pool32f_nanomips_insn(ctx);
break;
case NM_POOL32S:
break;
--
1.9.1
next prev parent reply other threads:[~2018-06-20 12:09 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 12:05 [Qemu-devel] [PATCH 00/35] nanoMIPS Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 01/35] target/mips: Raise a RI when given fs is n/a from CTC1 Yongbok Kim
2018-06-22 13:45 ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 02/35] target/mips: Fix microMIPS on reset Yongbok Kim
2018-06-22 13:45 ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 03/35] target/mips: Add nanoMIPS OPCODE table Yongbok Kim
2018-06-21 23:15 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 04/35] target/mips: Add decode_nanomips_opc() Yongbok Kim
2018-06-21 23:39 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 05/35] target/mips: Add nanoMIPS 16bit ld/st instructions Yongbok Kim
2018-06-21 23:48 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 06/35] target/mips: Add nanoMIPS pool16c instructions Yongbok Kim
2018-06-22 3:40 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 07/35] target/mips: Add nanoMIPS save and restore Yongbok Kim
2018-06-22 5:11 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 08/35] target/mips: Add nanoMIPS 32bit instructions Yongbok Kim
2018-06-24 23:32 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 09/35] target/mips: Add nanoMIPS 48bit instructions Yongbok Kim
2018-06-24 23:49 ` Richard Henderson
2018-06-20 12:05 ` Yongbok Kim [this message]
2018-06-20 12:05 ` [Qemu-devel] [PATCH 11/35] target/mips: Add nanoMIPS pool32a0 instructions Yongbok Kim
2018-06-24 23:59 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 12/35] target/mips: Add nanoMIPS pool32axf instructions Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst() Yongbok Kim
2018-06-22 4:13 ` Philippe Mathieu-Daudé
2018-06-22 13:46 ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions Yongbok Kim
2018-06-25 0:07 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 15/35] target/mips: Implement nanoMIPS EXTW instruction Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions Yongbok Kim
2018-06-25 0:23 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair Yongbok Kim
2018-06-25 0:27 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 20/35] target/mips: Fix not to update BadVAddr in Debug Mode Yongbok Kim
2018-06-22 4:15 ` Philippe Mathieu-Daudé
2018-06-20 12:06 ` [Qemu-devel] [PATCH 21/35] target/mips: Add nanoMIPS rotx instruction Yongbok Kim
2018-06-25 0:30 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset Yongbok Kim
2018-06-22 4:16 ` Philippe Mathieu-Daudé
2018-06-22 13:47 ` Aleksandar Markovic
2018-06-20 12:06 ` [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 26/35] target/mips: Fix nanoMIPS exception_resume_pc Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception Yongbok Kim
2018-06-22 4:31 ` Philippe Mathieu-Daudé
2018-06-20 12:06 ` [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers Yongbok Kim
2018-06-22 13:47 ` Aleksandar Markovic
2018-06-20 12:06 ` [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU Yongbok Kim
2018-06-22 4:26 ` [Qemu-devel] [PATCH 00/35] nanoMIPS Philippe Mathieu-Daudé
2018-06-22 14:39 ` Aleksandar Markovic
2018-06-22 15:16 ` Philippe Mathieu-Daudé
2018-06-22 15:31 ` Peter Maydell
2018-06-22 14:21 ` Aleksandar Markovic
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