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From: Yongbok Kim <yongbok.kim@mips.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Aleksandar.Markovic@mips.com,
	James.Hogan@mips.com, Paul.Burton@mips.com,
	Matthew.Fortune@mips.com, Stefan.Markovic@mips.com
Subject: [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader
Date: Wed, 20 Jun 2018 13:06:16 +0100	[thread overview]
Message-ID: <20180620120620.12806-32-yongbok.kim@mips.com> (raw)
In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com>

From: Paul Burton <paul.burton@imgtec.com>

Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
---
 hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 39f4c5b..c4139d6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -663,6 +663,79 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
                                 /* lui a3,%hi(loaderparams.ram_low_size) */
     stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
                                 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
+
+    /* Load BAR registers as done by YAMON */
+    stw_p(p++, 0xe040); stw_p(p++, 0x0681);
+                                /* lui t1, %hi(0xb4000000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
+                                /* lui t0, %hi(0xdf000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x00df);
+                                /* addiu[32] t0, $0, 0xdf */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
+                                /* sw t0, 0x68(t1) */
+
+    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
+                                /* lui t1, %hi(0xbbe00000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x0801);
+                                /* lui t0, %hi(0xc0000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
+                                /* addiu[32] t0, $0, 0xc0 */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
+                                /* sw t0, 0x48(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
+                                /* lui t0, %hi(0x40000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
+                                /* addiu[32] t0, $0, 0x40 */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
+                                /* sw t0, 0x50(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
+                                /* lui t0, %hi(0x80000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
+                                /* addiu[32] t0, $0, 0x80 */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
+                                /* sw t0, 0x58(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
+                                /* lui t0, %hi(0x3f000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x003f);
+                                /* addiu[32] t0, $0, 0x3f */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
+                                /* sw t0, 0x60(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x0821);
+                                /* lui t0, %hi(0xc1000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
+                                /* addiu[32] t0, $0, 0xc1 */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
+                                /* sw t0, 0x80(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
+                                /* lui t0, %hi(0x5e000000) */
+#else
+    stw_p(p++, 0x0020); stw_p(p++, 0x005e);
+                                /* addiu[32] t0, $0, 0x5e */
+#endif
+    stw_p(p++, 0x8422); stw_p(p++, 0x9088);
+                                /* sw t0, 0x88(t1) */
+
     stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
     stw_p(p++, NM_HI2(kernel_entry));
                                 /* lui t9,%hi(kernel_entry) */
-- 
1.9.1

  parent reply	other threads:[~2018-06-20 12:15 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-20 12:05 [Qemu-devel] [PATCH 00/35] nanoMIPS Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 01/35] target/mips: Raise a RI when given fs is n/a from CTC1 Yongbok Kim
2018-06-22 13:45   ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 02/35] target/mips: Fix microMIPS on reset Yongbok Kim
2018-06-22 13:45   ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 03/35] target/mips: Add nanoMIPS OPCODE table Yongbok Kim
2018-06-21 23:15   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 04/35] target/mips: Add decode_nanomips_opc() Yongbok Kim
2018-06-21 23:39   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 05/35] target/mips: Add nanoMIPS 16bit ld/st instructions Yongbok Kim
2018-06-21 23:48   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 06/35] target/mips: Add nanoMIPS pool16c instructions Yongbok Kim
2018-06-22  3:40   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 07/35] target/mips: Add nanoMIPS save and restore Yongbok Kim
2018-06-22  5:11   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 08/35] target/mips: Add nanoMIPS 32bit instructions Yongbok Kim
2018-06-24 23:32   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 09/35] target/mips: Add nanoMIPS 48bit instructions Yongbok Kim
2018-06-24 23:49   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 10/35] target/mips: Add nanoMIPS pool32f instructions Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 11/35] target/mips: Add nanoMIPS pool32a0 instructions Yongbok Kim
2018-06-24 23:59   ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 12/35] target/mips: Add nanoMIPS pool32axf instructions Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst() Yongbok Kim
2018-06-22  4:13   ` Philippe Mathieu-Daudé
2018-06-22 13:46   ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions Yongbok Kim
2018-06-25  0:07   ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 15/35] target/mips: Implement nanoMIPS EXTW instruction Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions Yongbok Kim
2018-06-25  0:23   ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair Yongbok Kim
2018-06-25  0:27   ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 20/35] target/mips: Fix not to update BadVAddr in Debug Mode Yongbok Kim
2018-06-22  4:15   ` Philippe Mathieu-Daudé
2018-06-20 12:06 ` [Qemu-devel] [PATCH 21/35] target/mips: Add nanoMIPS rotx instruction Yongbok Kim
2018-06-25  0:30   ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset Yongbok Kim
2018-06-22  4:16   ` Philippe Mathieu-Daudé
2018-06-22 13:47   ` Aleksandar Markovic
2018-06-20 12:06 ` [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 26/35] target/mips: Fix nanoMIPS exception_resume_pc Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception Yongbok Kim
2018-06-22  4:31   ` Philippe Mathieu-Daudé
2018-06-20 12:06 ` [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code Yongbok Kim
2018-06-20 12:06 ` Yongbok Kim [this message]
2018-06-20 12:06 ` [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers Yongbok Kim
2018-06-22 13:47   ` Aleksandar Markovic
2018-06-20 12:06 ` [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU Yongbok Kim
2018-06-22  4:26 ` [Qemu-devel] [PATCH 00/35] nanoMIPS Philippe Mathieu-Daudé
2018-06-22 14:39   ` Aleksandar Markovic
2018-06-22 15:16     ` Philippe Mathieu-Daudé
2018-06-22 15:31       ` Peter Maydell
2018-06-22 14:21 ` Aleksandar Markovic

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