From: Yongbok Kim <yongbok.kim@mips.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Aleksandar.Markovic@mips.com,
James.Hogan@mips.com, Paul.Burton@mips.com,
Matthew.Fortune@mips.com, Stefan.Markovic@mips.com
Subject: [Qemu-devel] [PATCH 04/35] target/mips: Add decode_nanomips_opc()
Date: Wed, 20 Jun 2018 13:05:49 +0100 [thread overview]
Message-ID: <20180620120620.12806-5-yongbok.kim@mips.com> (raw)
In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com>
Add nanoMIPS decoder.
It covers P16 pool arithmetic and branch instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
---
target/mips/translate.c | 293 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 292 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 27d5fb2..633d0b4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16200,6 +16200,293 @@ enum {
NM_EVP = 0x01
};
+static int mmreg_nanomips(int r)
+{
+ static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 };
+
+ return map[r & 0x7];
+}
+
+static int mmreg4_nanomips(int r)
+{
+ static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7,
+ 16, 17, 18, 19, 20, 21, 22, 23 };
+
+ return map[r & 0xf];
+}
+
+/* Used for 16-bit store instructions. */
+static int mmreg4z_nanomips(int r)
+{
+ static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7,
+ 16, 17, 18, 19, 20, 21, 22, 23 };
+
+ return map[r & 0xf];
+}
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t op;
+ int rt = mmreg_nanomips(uMIPS_RD(ctx->opcode));
+ int rs = mmreg_nanomips(uMIPS_RS(ctx->opcode));
+ int rd = mmreg_nanomips(uMIPS_RS1(ctx->opcode));
+
+ /* make sure instructions are on a halfword boundary */
+ if (ctx->base.pc_next & 0x1) {
+ env->CP0_BadVAddr = ctx->base.pc_next;
+ generate_exception_end(ctx, EXCP_AdEL);
+ return 2;
+ }
+
+ op = (ctx->opcode >> 10) & 0x3f;
+ switch (op) {
+ case NM_P16_MV:
+ {
+ int rt = uMIPS_RD5(ctx->opcode);
+ if (rt != 0) {
+ /* MOVE */
+ int rs = uMIPS_RS5(ctx->opcode);
+ gen_arith(ctx, OPC_ADDU, rt, rs, 0);
+ } else {
+ /* P16.RI */
+ switch ((ctx->opcode >> 3) & 0x3) {
+ case NM_P16_SYSCALL:
+ generate_exception_end(ctx, EXCP_SYSCALL);
+ break;
+ case NM_BREAK16:
+ generate_exception_end(ctx, EXCP_BREAK);
+ break;
+ case NM_SDBBP16:
+ if (is_uhi(extract32(ctx->opcode, 0, 3))) {
+ gen_helper_do_semihosting(cpu_env);
+ } else {
+ if (ctx->hflags & MIPS_HFLAG_SBRI) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else {
+ generate_exception_end(ctx, EXCP_DBp);
+ }
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
+ }
+ break;
+ case NM_P16_SHIFT:
+ {
+ int shift = (ctx->opcode) & 0x7;
+ uint32_t opc = 0;
+ shift = (shift == 0) ? 8 : shift;
+
+ switch ((ctx->opcode >> 3) & 1) {
+ case NM_SLL16:
+ opc = OPC_SLL;
+ break;
+ case NM_SRL16:
+ opc = OPC_SRL;
+ break;
+ }
+ gen_shift_imm(ctx, opc, rt, rs, shift);
+ }
+ break;
+ case NM_P16C:
+ break;
+ case NM_P16_A1:
+ switch ((ctx->opcode >> 6) & 1) {
+ case NM_ADDIUR1SP:
+ gen_arith_imm(ctx, OPC_ADDIU, rt, 29,
+ extract32(ctx->opcode, 0, 6) << 2);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P16_A2:
+ switch ((ctx->opcode >> 3) & 1) {
+ case NM_ADDIUR2:
+ {
+ uint8_t u = (uint8_t) extract32(ctx->opcode, 0, 3) << 2;
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u);
+ }
+ break;
+ case NM_P_ADDIURS5:
+ {
+ int rt = extract32(ctx->opcode, 5, 5);
+ if (rt != 0) {
+ int s = (sextract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ /* s = sign_extend( s[3] . s[2:0] , from_nbits = 4)*/
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rt, s);
+ }
+ }
+ break;
+ }
+ break;
+ case NM_P16_ADDU:
+ switch (ctx->opcode & 0x1) {
+ case NM_ADDU16:
+ gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+ break;
+ case NM_SUBU16:
+ gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+ break;
+ }
+ break;
+ case NM_P16_4X4:
+ {
+ int rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+ int rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ rt = mmreg4_nanomips(rt);
+ rs = mmreg4_nanomips(rs);
+
+ switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1)) {
+ case NM_ADDU4X4:
+ gen_arith(ctx, OPC_ADDU, rt, rs, rt);
+ break;
+ case NM_MUL4X4:
+ gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ }
+ break;
+ case NM_LI16:
+ {
+ int imm = extract32(ctx->opcode, 0, 7);
+ imm = (imm == 0x7f ? -1 : imm);
+ if (rt != 0) {
+ tcg_gen_movi_tl(cpu_gpr[rt], imm);
+ }
+ }
+ break;
+ case NM_ANDI16:
+ {
+ uint32_t u = extract32(ctx->opcode, 0, 4);
+ u = (u == 12) ? 0xff :
+ (u == 13) ? 0xffff : u;
+ gen_logic_imm(ctx, OPC_ANDI, rt, rs, u);
+ }
+ break;
+ case NM_P16_LB:
+ break;
+ case NM_P16_LH:
+ break;
+ case NM_LW16:
+ break;
+ case NM_LWSP16:
+ break;
+ case NM_LW4X4:
+ break;
+ case NM_SW4X4:
+ break;
+ case NM_LWGP16:
+ break;
+ case NM_SWSP16:
+ break;
+ case NM_SW16:
+ break;
+ case NM_SWGP16:
+ break;
+ case NM_BC16:
+ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
+ (sextract32(ctx->opcode, 0, 1) << 10) |
+ (extract32(ctx->opcode, 1, 9) << 1),
+ 0);
+ break;
+ case NM_BALC16:
+ gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0,
+ (sextract32(ctx->opcode, 0, 1) << 10) |
+ (extract32(ctx->opcode, 1, 9) << 1),
+ 0);
+ break;
+ case NM_BEQZC16:
+ case NM_BNEZC16:
+ gen_compute_branch(ctx, op == NM_BNEZC16 ? OPC_BNE : OPC_BEQ, 2,
+ rt, 0,
+ (sextract32(ctx->opcode, 0, 1) << 7) |
+ (extract32(ctx->opcode, 1, 6) << 1),
+ 0);
+ break;
+ case NM_P16_BR:
+ switch (ctx->opcode & 0xf) {
+ case 0:
+ /* P16.JRC */
+ switch ((ctx->opcode >> 4) & 1) {
+ case NM_JRC:
+ gen_compute_branch(ctx, OPC_JR, 2,
+ extract32(ctx->opcode, 5, 5), 0, 0, 0);
+ break;
+ case NM_JALRC16:
+ gen_compute_branch(ctx, OPC_JALR, 2,
+ extract32(ctx->opcode, 5, 5), 31, 0, 0);
+ break;
+ }
+ break;
+ default:
+ /* P16.BRI */
+ if (extract32(ctx->opcode, 4, 3) < extract32(ctx->opcode, 7, 3)) {
+ /* BEQC16 */
+ gen_compute_branch(ctx, OPC_BEQ, 2, rs, rt,
+ extract32(ctx->opcode, 0, 4) << 1, 0);
+ } else {
+ /* BNEC16 */
+ gen_compute_branch(ctx, OPC_BNE, 2, rs, rt,
+ extract32(ctx->opcode, 0, 4) << 1, 0);
+ }
+ break;
+ }
+ break;
+ case NM_P16_SR:
+ break;
+ case NM_MOVEP:
+ case NM_MOVEPREV:
+ {
+ static const int gpr2reg1[] = {4, 5, 6, 7};
+ static const int gpr2reg2[] = {5, 6, 7, 8};
+ int re;
+ int rd2 = extract32(ctx->opcode, 3, 1) << 1 |
+ extract32(ctx->opcode, 8, 1);
+ int r1 = gpr2reg1[rd2];
+ int r2 = gpr2reg2[rd2];
+ int r3 = extract32(ctx->opcode, 4, 1) << 3 |
+ extract32(ctx->opcode, 0, 3);
+ int r4 = extract32(ctx->opcode, 9, 1) << 3 |
+ extract32(ctx->opcode, 5, 3);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ if (op == NM_MOVEP) {
+ rd = r1;
+ re = r2;
+ rs = mmreg4z_nanomips(r3);
+ rt = mmreg4z_nanomips(r4);
+ } else {
+ rd = mmreg4_nanomips(r3);
+ re = mmreg4_nanomips(r4);
+ rs = r1;
+ rt = r2;
+ }
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_mov_tl(cpu_gpr[rd], t0);
+ tcg_gen_mov_tl(cpu_gpr[re], t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return 2;
+}
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -20950,7 +21237,11 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
decode_opc(env, ctx);
} else if (ctx->insn_flags & ASE_MICROMIPS) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
- insn_bytes = decode_micromips_opc(env, ctx);
+ if (env->insn_flags & ISA_NANOMIPS32) {
+ insn_bytes = decode_nanomips_opc(env, ctx);
+ } else {
+ insn_bytes = decode_micromips_opc(env, ctx);
+ }
} else if (ctx->insn_flags & ASE_MIPS16) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_mips16_opc(env, ctx);
--
1.9.1
next prev parent reply other threads:[~2018-06-20 12:07 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 12:05 [Qemu-devel] [PATCH 00/35] nanoMIPS Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 01/35] target/mips: Raise a RI when given fs is n/a from CTC1 Yongbok Kim
2018-06-22 13:45 ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 02/35] target/mips: Fix microMIPS on reset Yongbok Kim
2018-06-22 13:45 ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 03/35] target/mips: Add nanoMIPS OPCODE table Yongbok Kim
2018-06-21 23:15 ` Richard Henderson
2018-06-20 12:05 ` Yongbok Kim [this message]
2018-06-21 23:39 ` [Qemu-devel] [PATCH 04/35] target/mips: Add decode_nanomips_opc() Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 05/35] target/mips: Add nanoMIPS 16bit ld/st instructions Yongbok Kim
2018-06-21 23:48 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 06/35] target/mips: Add nanoMIPS pool16c instructions Yongbok Kim
2018-06-22 3:40 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 07/35] target/mips: Add nanoMIPS save and restore Yongbok Kim
2018-06-22 5:11 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 08/35] target/mips: Add nanoMIPS 32bit instructions Yongbok Kim
2018-06-24 23:32 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 09/35] target/mips: Add nanoMIPS 48bit instructions Yongbok Kim
2018-06-24 23:49 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 10/35] target/mips: Add nanoMIPS pool32f instructions Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 11/35] target/mips: Add nanoMIPS pool32a0 instructions Yongbok Kim
2018-06-24 23:59 ` Richard Henderson
2018-06-20 12:05 ` [Qemu-devel] [PATCH 12/35] target/mips: Add nanoMIPS pool32axf instructions Yongbok Kim
2018-06-20 12:05 ` [Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst() Yongbok Kim
2018-06-22 4:13 ` Philippe Mathieu-Daudé
2018-06-22 13:46 ` Aleksandar Markovic
2018-06-20 12:05 ` [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions Yongbok Kim
2018-06-25 0:07 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 15/35] target/mips: Implement nanoMIPS EXTW instruction Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions Yongbok Kim
2018-06-25 0:23 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair Yongbok Kim
2018-06-25 0:27 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 20/35] target/mips: Fix not to update BadVAddr in Debug Mode Yongbok Kim
2018-06-22 4:15 ` Philippe Mathieu-Daudé
2018-06-20 12:06 ` [Qemu-devel] [PATCH 21/35] target/mips: Add nanoMIPS rotx instruction Yongbok Kim
2018-06-25 0:30 ` Richard Henderson
2018-06-20 12:06 ` [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset Yongbok Kim
2018-06-22 4:16 ` Philippe Mathieu-Daudé
2018-06-22 13:47 ` Aleksandar Markovic
2018-06-20 12:06 ` [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 26/35] target/mips: Fix nanoMIPS exception_resume_pc Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 27/35] target/mips: Fix nanoMIPS set_hflags_for_handler Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 28/35] target/mips: Fix nanoMIPS set_pc Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception Yongbok Kim
2018-06-22 4:31 ` Philippe Mathieu-Daudé
2018-06-20 12:06 ` [Qemu-devel] [PATCH 30/35] hw/mips: Add basic nanoMIPS boot code Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers Yongbok Kim
2018-06-22 13:47 ` Aleksandar Markovic
2018-06-20 12:06 ` [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit Yongbok Kim
2018-06-20 12:06 ` [Qemu-devel] [PATCH 35/35] target/mips: Add I7200 CPU Yongbok Kim
2018-06-22 4:26 ` [Qemu-devel] [PATCH 00/35] nanoMIPS Philippe Mathieu-Daudé
2018-06-22 14:39 ` Aleksandar Markovic
2018-06-22 15:16 ` Philippe Mathieu-Daudé
2018-06-22 15:31 ` Peter Maydell
2018-06-22 14:21 ` Aleksandar Markovic
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