From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v5 14/35] target/arm: Implement SVE first-fault gather loads
Date: Wed, 20 Jun 2018 15:53:38 -1000 [thread overview]
Message-ID: <20180621015359.12018-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180621015359.12018-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 67 ++++++++++++++++++++
target/arm/sve_helper.c | 88 ++++++++++++++++++++++++++
target/arm/translate-sve.c | 126 ++++++++++++++++++++++++-------------
3 files changed, 236 insertions(+), 45 deletions(-)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index aeb62afc34..55e8a908d4 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -1026,6 +1026,73 @@ DEF_HELPER_FLAGS_6(sve_ldhds_zd, TCG_CALL_NO_WG,
DEF_HELPER_FLAGS_6(sve_ldsds_zd, TCG_CALL_NO_WG,
void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffbsu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhsu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffssu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffbss_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhss_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_6(sve_ldffbsu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhsu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffssu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffbss_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhss_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_6(sve_ldffbdu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhdu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffsdu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffddu_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffbds_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhds_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffsds_zsu, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_6(sve_ldffbdu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhdu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffsdu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffddu_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffbds_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhds_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffsds_zss, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_6(sve_ldffbdu_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhdu_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffsdu_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffddu_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffbds_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffhds_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_6(sve_ldffsds_zd, TCG_CALL_NO_WG,
+ void, env, ptr, ptr, ptr, tl, i32)
+
DEF_HELPER_FLAGS_6(sve_stbs_zsu, TCG_CALL_NO_WG,
void, env, ptr, ptr, ptr, tl, i32)
DEF_HELPER_FLAGS_6(sve_sths_zsu, TCG_CALL_NO_WG,
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 9b99718156..38f7cc2274 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3790,6 +3790,94 @@ DO_LD1_ZPZ_D(sve_ldbds_zd, uint64_t, int8_t, cpu_ldub_data_ra)
DO_LD1_ZPZ_D(sve_ldhds_zd, uint64_t, int16_t, cpu_lduw_data_ra)
DO_LD1_ZPZ_D(sve_ldsds_zd, uint64_t, int32_t, cpu_ldl_data_ra)
+/* First fault loads with a vector index. */
+
+#ifdef CONFIG_USER_ONLY
+
+#define DO_LDFF1_ZPZ(NAME, TYPEE, TYPEI, TYPEM, FN, H) \
+void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
+ target_ulong base, uint32_t desc) \
+{ \
+ intptr_t i, oprsz = simd_oprsz(desc); \
+ unsigned scale = simd_data(desc); \
+ uintptr_t ra = GETPC(); \
+ bool first = true; \
+ mmap_lock(); \
+ for (i = 0; i < oprsz; i++) { \
+ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
+ do { \
+ TYPEM m = 0; \
+ if (pg & 1) { \
+ target_ulong off = *(TYPEI *)(vm + H(i)); \
+ target_ulong addr = base + (off << scale); \
+ if (!first && \
+ page_check_range(addr, sizeof(TYPEM), PAGE_READ)) { \
+ record_fault(env, i, oprsz); \
+ goto exit; \
+ } \
+ m = FN(env, addr, ra); \
+ first = false; \
+ } \
+ *(TYPEE *)(vd + H(i)) = m; \
+ i += sizeof(TYPEE), pg >>= sizeof(TYPEE); \
+ } while (i & 15); \
+ } \
+ exit: \
+ mmap_unlock(); \
+}
+
+#else
+
+#define DO_LDFF1_ZPZ(NAME, TYPEE, TYPEI, TYPEM, FN, H) \
+void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
+ target_ulong base, uint32_t desc) \
+{ \
+ g_assert_not_reached(); \
+}
+
+#endif
+
+#define DO_LDFF1_ZPZ_S(NAME, TYPEI, TYPEM, FN) \
+ DO_LDFF1_ZPZ(NAME, uint32_t, TYPEI, TYPEM, FN, H1_4)
+#define DO_LDFF1_ZPZ_D(NAME, TYPEI, TYPEM, FN) \
+ DO_LDFF1_ZPZ(NAME, uint64_t, TYPEI, TYPEM, FN, )
+
+DO_LDFF1_ZPZ_S(sve_ldffbsu_zsu, uint32_t, uint8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffhsu_zsu, uint32_t, uint16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffssu_zsu, uint32_t, uint32_t, cpu_ldl_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffbss_zsu, uint32_t, int8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffhss_zsu, uint32_t, int16_t, cpu_lduw_data_ra)
+
+DO_LDFF1_ZPZ_S(sve_ldffbsu_zss, int32_t, uint8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffhsu_zss, int32_t, uint16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffssu_zss, int32_t, uint32_t, cpu_ldl_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffbss_zss, int32_t, int8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_S(sve_ldffhss_zss, int32_t, int16_t, cpu_lduw_data_ra)
+
+DO_LDFF1_ZPZ_D(sve_ldffbdu_zsu, uint32_t, uint8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffhdu_zsu, uint32_t, uint16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffsdu_zsu, uint32_t, uint32_t, cpu_ldl_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffddu_zsu, uint32_t, uint64_t, cpu_ldq_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffbds_zsu, uint32_t, int8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffhds_zsu, uint32_t, int16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffsds_zsu, uint32_t, int32_t, cpu_ldl_data_ra)
+
+DO_LDFF1_ZPZ_D(sve_ldffbdu_zss, int32_t, uint8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffhdu_zss, int32_t, uint16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffsdu_zss, int32_t, uint32_t, cpu_ldl_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffddu_zss, int32_t, uint64_t, cpu_ldq_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffbds_zss, int32_t, int8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffhds_zss, int32_t, int16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffsds_zss, int32_t, int32_t, cpu_ldl_data_ra)
+
+DO_LDFF1_ZPZ_D(sve_ldffbdu_zd, uint64_t, uint8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffhdu_zd, uint64_t, uint16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffsdu_zd, uint64_t, uint32_t, cpu_ldl_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffddu_zd, uint64_t, uint64_t, cpu_ldq_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffbds_zd, uint64_t, int8_t, cpu_ldub_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffhds_zd, uint64_t, int16_t, cpu_lduw_data_ra)
+DO_LDFF1_ZPZ_D(sve_ldffsds_zd, uint64_t, int32_t, cpu_ldl_data_ra)
+
/* Stores with a vector index. */
#define DO_ST1_ZPZ_S(NAME, TYPEI, FN) \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index a53554f8d5..11c1bf112c 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4255,47 +4255,85 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, int scale,
tcg_temp_free_i32(desc);
}
-/* Indexed by [xs][u][msz]. */
-static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][3] = {
- { { gen_helper_sve_ldbss_zsu,
- gen_helper_sve_ldhss_zsu,
- NULL, },
- { gen_helper_sve_ldbsu_zsu,
- gen_helper_sve_ldhsu_zsu,
- gen_helper_sve_ldssu_zsu, } },
- { { gen_helper_sve_ldbss_zss,
- gen_helper_sve_ldhss_zss,
- NULL, },
- { gen_helper_sve_ldbsu_zss,
- gen_helper_sve_ldhsu_zss,
- gen_helper_sve_ldssu_zss, } },
+/* Indexed by [ff][xs][u][msz]. */
+static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][2][3] = {
+ { { { gen_helper_sve_ldbss_zsu,
+ gen_helper_sve_ldhss_zsu,
+ NULL, },
+ { gen_helper_sve_ldbsu_zsu,
+ gen_helper_sve_ldhsu_zsu,
+ gen_helper_sve_ldssu_zsu, } },
+ { { gen_helper_sve_ldbss_zss,
+ gen_helper_sve_ldhss_zss,
+ NULL, },
+ { gen_helper_sve_ldbsu_zss,
+ gen_helper_sve_ldhsu_zss,
+ gen_helper_sve_ldssu_zss, } }, },
+
+ { { { gen_helper_sve_ldffbss_zsu,
+ gen_helper_sve_ldffhss_zsu,
+ NULL, },
+ { gen_helper_sve_ldffbsu_zsu,
+ gen_helper_sve_ldffhsu_zsu,
+ gen_helper_sve_ldffssu_zsu, } },
+ { { gen_helper_sve_ldffbss_zss,
+ gen_helper_sve_ldffhss_zss,
+ NULL, },
+ { gen_helper_sve_ldffbsu_zss,
+ gen_helper_sve_ldffhsu_zss,
+ gen_helper_sve_ldffssu_zss, } } }
};
-static gen_helper_gvec_mem_scatter * const gather_load_fn64[3][2][4] = {
- { { gen_helper_sve_ldbds_zsu,
- gen_helper_sve_ldhds_zsu,
- gen_helper_sve_ldsds_zsu,
- NULL, },
- { gen_helper_sve_ldbdu_zsu,
- gen_helper_sve_ldhdu_zsu,
- gen_helper_sve_ldsdu_zsu,
- gen_helper_sve_ldddu_zsu, } },
- { { gen_helper_sve_ldbds_zss,
- gen_helper_sve_ldhds_zss,
- gen_helper_sve_ldsds_zss,
- NULL, },
- { gen_helper_sve_ldbdu_zss,
- gen_helper_sve_ldhdu_zss,
- gen_helper_sve_ldsdu_zss,
- gen_helper_sve_ldddu_zss, } },
- { { gen_helper_sve_ldbds_zd,
- gen_helper_sve_ldhds_zd,
- gen_helper_sve_ldsds_zd,
- NULL, },
- { gen_helper_sve_ldbdu_zd,
- gen_helper_sve_ldhdu_zd,
- gen_helper_sve_ldsdu_zd,
- gen_helper_sve_ldddu_zd, } },
+static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][3][2][4] = {
+ { { { gen_helper_sve_ldbds_zsu,
+ gen_helper_sve_ldhds_zsu,
+ gen_helper_sve_ldsds_zsu,
+ NULL, },
+ { gen_helper_sve_ldbdu_zsu,
+ gen_helper_sve_ldhdu_zsu,
+ gen_helper_sve_ldsdu_zsu,
+ gen_helper_sve_ldddu_zsu, } },
+ { { gen_helper_sve_ldbds_zss,
+ gen_helper_sve_ldhds_zss,
+ gen_helper_sve_ldsds_zss,
+ NULL, },
+ { gen_helper_sve_ldbdu_zss,
+ gen_helper_sve_ldhdu_zss,
+ gen_helper_sve_ldsdu_zss,
+ gen_helper_sve_ldddu_zss, } },
+ { { gen_helper_sve_ldbds_zd,
+ gen_helper_sve_ldhds_zd,
+ gen_helper_sve_ldsds_zd,
+ NULL, },
+ { gen_helper_sve_ldbdu_zd,
+ gen_helper_sve_ldhdu_zd,
+ gen_helper_sve_ldsdu_zd,
+ gen_helper_sve_ldddu_zd, } } },
+
+ { { { gen_helper_sve_ldffbds_zsu,
+ gen_helper_sve_ldffhds_zsu,
+ gen_helper_sve_ldffsds_zsu,
+ NULL, },
+ { gen_helper_sve_ldffbdu_zsu,
+ gen_helper_sve_ldffhdu_zsu,
+ gen_helper_sve_ldffsdu_zsu,
+ gen_helper_sve_ldffddu_zsu, } },
+ { { gen_helper_sve_ldffbds_zss,
+ gen_helper_sve_ldffhds_zss,
+ gen_helper_sve_ldffsds_zss,
+ NULL, },
+ { gen_helper_sve_ldffbdu_zss,
+ gen_helper_sve_ldffhdu_zss,
+ gen_helper_sve_ldffsdu_zss,
+ gen_helper_sve_ldffddu_zss, } },
+ { { gen_helper_sve_ldffbds_zd,
+ gen_helper_sve_ldffhds_zd,
+ gen_helper_sve_ldffsds_zd,
+ NULL, },
+ { gen_helper_sve_ldffbdu_zd,
+ gen_helper_sve_ldffhdu_zd,
+ gen_helper_sve_ldffsdu_zd,
+ gen_helper_sve_ldffddu_zd, } } }
};
static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
@@ -4311,13 +4349,12 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
return true;
}
- /* TODO: handle LDFF1. */
switch (a->esz) {
case MO_32:
- fn = gather_load_fn32[a->xs][a->u][a->msz];
+ fn = gather_load_fn32[a->ff][a->xs][a->u][a->msz];
break;
case MO_64:
- fn = gather_load_fn64[a->xs][a->u][a->msz];
+ fn = gather_load_fn64[a->ff][a->xs][a->u][a->msz];
break;
}
assert(fn != NULL);
@@ -4339,13 +4376,12 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a, uint32_t insn)
return true;
}
- /* TODO: handle LDFF1. */
switch (a->esz) {
case MO_32:
- fn = gather_load_fn32[0][a->u][a->msz];
+ fn = gather_load_fn32[a->ff][0][a->u][a->msz];
break;
case MO_64:
- fn = gather_load_fn64[2][a->u][a->msz];
+ fn = gather_load_fn64[a->ff][2][a->u][a->msz];
break;
}
assert(fn != NULL);
--
2.17.1
next prev parent reply other threads:[~2018-06-21 1:54 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-21 1:53 [Qemu-devel] [PATCH v5 00/35] target/arm SVE patches Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 01/35] target/arm: Implement SVE Memory Contiguous Load Group Richard Henderson
2018-06-22 15:29 ` Peter Maydell
2018-06-26 9:55 ` Alex Bennée
2018-06-26 14:04 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 02/35] target/arm: Implement SVE Contiguous Load, first-fault and no-fault Richard Henderson
2018-06-22 16:04 ` Peter Maydell
2018-06-22 18:37 ` Richard Henderson
2018-06-26 12:52 ` Alex Bennée
2018-06-26 14:06 ` Richard Henderson
2018-06-27 11:37 ` Alex Bennée
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 03/35] target/arm: Implement SVE Memory Contiguous Store Group Richard Henderson
2018-06-25 15:03 ` Peter Maydell
2018-06-27 11:38 ` Alex Bennée
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 04/35] target/arm: Implement SVE load and broadcast quadword Richard Henderson
2018-06-25 15:08 ` Peter Maydell
2018-06-27 14:05 ` Alex Bennée
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 05/35] target/arm: Implement SVE integer convert to floating-point Richard Henderson
2018-06-25 15:21 ` Peter Maydell
2018-06-27 14:19 ` Alex Bennée
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 06/35] target/arm: Implement SVE floating-point arithmetic (predicated) Richard Henderson
2018-06-25 15:24 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 07/35] target/arm: Implement SVE FP Multiply-Add Group Richard Henderson
2018-06-25 15:32 ` Peter Maydell
2018-06-26 14:08 ` Richard Henderson
2018-06-26 14:11 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 08/35] target/arm: Implement SVE Floating Point Accumulating Reduction Group Richard Henderson
2018-06-25 15:35 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 09/35] target/arm: Implement SVE load and broadcast element Richard Henderson
2018-06-25 15:46 ` Peter Maydell
2018-06-26 14:10 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 10/35] target/arm: Implement SVE store vector/predicate register Richard Henderson
2018-06-25 15:51 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 11/35] target/arm: Implement SVE scatter stores Richard Henderson
2018-06-25 16:13 ` Peter Maydell
2018-06-26 14:21 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 12/35] target/arm: Implement SVE prefetches Richard Henderson
2018-06-25 16:18 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 13/35] target/arm: Implement SVE gather loads Richard Henderson
2018-06-25 16:55 ` Peter Maydell
2018-06-26 14:39 ` Richard Henderson
2018-06-21 1:53 ` Richard Henderson [this message]
2018-06-25 16:57 ` [Qemu-devel] [PATCH v5 14/35] target/arm: Implement SVE first-fault " Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 15/35] target/arm: Implement SVE scatter store vector immediate Richard Henderson
2018-06-25 17:00 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 16/35] target/arm: Implement SVE floating-point compare vectors Richard Henderson
2018-06-25 17:20 ` Peter Maydell
2018-06-26 16:41 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 17/35] target/arm: Implement SVE floating-point arithmetic with immediate Richard Henderson
2018-06-25 17:27 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 18/35] target/arm: Implement SVE Floating Point Multiply Indexed Group Richard Henderson
2018-06-25 17:47 ` Peter Maydell
2018-06-26 14:50 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 19/35] target/arm: Implement SVE FP Fast Reduction Group Richard Henderson
2018-06-26 10:09 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 20/35] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group Richard Henderson
2018-06-26 10:13 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 21/35] target/arm: Implement SVE FP Compare with Zero Group Richard Henderson
2018-06-26 10:18 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 22/35] target/arm: Implement SVE floating-point trig multiply-add coefficient Richard Henderson
2018-06-26 10:25 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 23/35] target/arm: Implement SVE floating-point convert precision Richard Henderson
2018-06-26 10:44 ` Peter Maydell
2018-06-27 4:02 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 24/35] target/arm: Implement SVE floating-point convert to integer Richard Henderson
2018-06-26 10:58 ` Peter Maydell
2018-06-26 18:24 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 25/35] target/arm: Implement SVE floating-point round to integral value Richard Henderson
2018-06-26 12:09 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 26/35] target/arm: Implement SVE floating-point unary operations Richard Henderson
2018-06-26 12:13 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 27/35] target/arm: Implement SVE MOVPRFX Richard Henderson
2018-06-26 12:24 ` Peter Maydell
2018-06-26 14:57 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 28/35] target/arm: Implement SVE floating-point complex add Richard Henderson
2018-06-26 13:17 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 29/35] target/arm: Implement SVE fp complex multiply add Richard Henderson
2018-06-26 13:29 ` Peter Maydell
2018-06-26 15:04 ` Richard Henderson
2018-06-26 15:17 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 30/35] target/arm: Pass index to AdvSIMD FCMLA (indexed) Richard Henderson
2018-06-26 13:38 ` Peter Maydell
2018-06-26 15:07 ` Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 31/35] target/arm: Implement SVE fp complex multiply add (indexed) Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 32/35] target/arm: Implement SVE dot product (vectors) Richard Henderson
2018-06-26 13:47 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 33/35] target/arm: Implement SVE dot product (indexed) Richard Henderson
2018-06-26 15:30 ` Peter Maydell
2018-06-26 16:17 ` Richard Henderson
2018-06-26 16:30 ` Peter Maydell
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 34/35] target/arm: Enable SVE for aarch64-linux-user Richard Henderson
2018-06-21 1:53 ` [Qemu-devel] [PATCH v5 35/35] target/arm: Implement ARMv8.2-DotProd Richard Henderson
2018-06-26 15:38 ` Peter Maydell
2018-06-21 5:18 ` [Qemu-devel] [PATCH v5 00/35] target/arm SVE patches no-reply
2018-06-26 9:41 ` Alex Bennée
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