From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWLd1-0003Ry-65 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 08:57:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWLcz-0005Ef-TN for qemu-devel@nongnu.org; Fri, 22 Jun 2018 08:57:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:42962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fWLcz-0005AA-IW for qemu-devel@nongnu.org; Fri, 22 Jun 2018 08:57:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fWLcy-0003vP-Fj for qemu-devel@nongnu.org; Fri, 22 Jun 2018 13:57:24 +0100 From: Peter Maydell Date: Fri, 22 Jun 2018 13:57:00 +0100 Message-Id: <20180622125713.15303-16-peter.maydell@linaro.org> In-Reply-To: <20180622125713.15303-1-peter.maydell@linaro.org> References: <20180622125713.15303-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 15/28] target-arm: Add the Cortex-R5F List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Add the Cortex-R5F with the optional FPU enabled. Reviewed-by: KONRAD Frederic Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias Message-id: 20180529124707.3025-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e1de45e904c..81c1d22b143 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1361,6 +1361,14 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } +static void cortex_r5f_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cortex_r5_initfn(obj); + set_feature(&cpu->env, ARM_FEATURE_VFP3); +} + static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -1821,6 +1829,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "cortex-m33", .initfn = cortex_m33_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-r5", .initfn = cortex_r5_initfn }, + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, { .name = "cortex-a7", .initfn = cortex_a7_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, -- 2.17.1