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From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [PATCH v3 1/5] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space
Date: Mon, 25 Jun 2018 17:00:05 +0100	[thread overview]
Message-ID: <20180625160009.17437-2-alex.bennee@linaro.org> (raw)
In-Reply-To: <20180625160009.17437-1-alex.bennee@linaro.org>

Since kernel commit a86bd139f2 (arm64: arch_timer: Enable CNTVCT_EL0
trap..) user-space has been able to read these system registers. As we
can't use QEMUTimer's in linux-user mode we just directly call
cpu_get_clock().

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
v2
  - include CNTFRQ_EL0 for PL0_R only
v3
  - use NANOSECONDS_PER_SECOND / GTIMER_SCALE
---
 target/arm/helper.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1248d84e6f..6e6b1762e8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2166,11 +2166,32 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
 };
 
 #else
-/* In user-mode none of the generic timer registers are accessible,
- * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
- * so instead just don't register any of them.
+
+/* In user-mode most of the generic timer registers are inaccessible
+ * however modern kernels (4.12+) allow access to cntvct_el0
  */
+
+static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /* Currently we have no support for QEMUTimer in linux-user so we
+     * can't call gt_get_countervalue(env), instead we directly
+     * call the lower level functions.
+     */
+    return cpu_get_clock() / GTIMER_SCALE;
+}
+
 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
+    { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
+      .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
+      .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
+    },
+    { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
+      .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
+      .readfn = gt_virt_cnt_read,
+    },
     REGINFO_SENTINEL
 };
 
-- 
2.17.1

  reply	other threads:[~2018-06-25 16:00 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-25 16:00 [Qemu-devel] [PATCH v3 0/5] support reading some CPUID/CNT registers from user-space Alex Bennée
2018-06-25 16:00 ` Alex Bennée [this message]
2018-06-27  4:52   ` [Qemu-devel] [PATCH v3 1/5] target/arm: support reading of CNT[VCT|FRQ]_EL0 " Richard Henderson
2018-06-27 16:57   ` Emilio G. Cota
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers Alex Bennée
2018-06-27  5:25   ` Richard Henderson
2018-06-28 14:25   ` Peter Maydell
2018-06-28 14:39     ` Alex Bennée
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 3/5] target/arm: expose CPUID registers to userspace Alex Bennée
2018-06-28 14:23   ` Peter Maydell
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 4/5] linux-user/elfload: enable HWCAP_CPUID for AArch64 Alex Bennée
2018-06-27  5:27   ` Richard Henderson
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 5/5] tests/tcg/aarch64: userspace system register test Alex Bennée
2018-06-25 20:51   ` Alex Bennée
2018-06-27  5:38   ` Richard Henderson
2018-06-28 15:06 ` [Qemu-devel] [PATCH v3 0/5] support reading some CPUID/CNT registers from user-space Peter Maydell

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