From: "Steffen Görtz" <contrib@steffen-goertz.de>
To: qemu-devel@nongnu.org
Cc: "Stefan Hajnoczi" <stefanha@gmail.com>,
"Joel Stanley" <joel@jms.id.au>,
"Jim Mussared" <jim@groklearning.com>,
"Julia Suvorova" <jusual@mail.ru>,
"Steffen Görtz" <contrib@steffen-goertz.de>,
"Peter Maydell" <peter.maydell@linaro.org>,
"open list:ARM" <qemu-arm@nongnu.org>
Subject: [Qemu-devel] [RFC 2/8] arm: NRF51 Add unimplemented device for MMIO
Date: Wed, 27 Jun 2018 09:33:45 +0200 [thread overview]
Message-ID: <20180627073351.856-3-contrib@steffen-goertz.de> (raw)
In-Reply-To: <20180627073351.856-1-contrib@steffen-goertz.de>
Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de>
---
hw/arm/nrf51_soc.c | 18 +++++++++++++-----
include/hw/arm/nrf51_soc.h | 4 +++-
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 1f7c159edf..175a009e65 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -48,7 +48,6 @@ struct {
{.ram_size = 32, .flash_size = 256 },
};
-
static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", __func__, addr, size);
@@ -125,6 +124,12 @@ static void nrf51_soc_init(Object *obj)
qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m3"));
+ object_initialize(&s->mmio, sizeof(s->mmio), TYPE_UNIMPLEMENTED_DEVICE);
+ object_property_add_child(obj, "iomem", OBJECT(&s->mmio), &error_abort);
+ qdev_set_parent_bus(DEVICE(&s->mmio), sysbus_get_default());
+ qdev_prop_set_string(DEVICE(&s->mmio), "name", "nrf51.iomem");
+ qdev_prop_set_uint64(DEVICE(&s->mmio), "size", IOMEM_SIZE);
+
object_initialize(&s->uart, sizeof(s->uart), TYPE_NRF51_UART);
object_property_add_child(obj, "uart", OBJECT(&s->uart), &error_abort);
qdev_set_parent_bus(DEVICE(&s->uart), sysbus_get_default());
@@ -135,6 +140,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
{
NRF51State *s = NRF51_SOC(dev_soc);
Error *err = NULL;
+ MemoryRegion *mr = NULL;
if (!(s->part_variant > NRF51_VARIANT_INVALID
&& s->part_variant < NRF51_VARIANT_MAX)) {
@@ -142,6 +148,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ /** SRAM **/
memory_region_init_ram(&s->sram, NULL, "nrf51_soc.sram",
NRF51VariantAttributes[s->part_variant].ram_size * PAGE_SIZE, &err);
if (err) {
@@ -150,6 +157,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
+ /** FLASH **/
memory_region_init_ram(&s->flash, NULL, "nrf51_soc.flash",
NRF51VariantAttributes[s->part_variant].flash_size * PAGE_SIZE,
&err);
@@ -159,6 +167,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
+ /** MCU **/
qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 60);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container),
"memory", &err);
@@ -175,10 +184,9 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
/* IO space */
- create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
-
- /* FICR */
- create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
+ object_property_set_bool(OBJECT(&s->mmio), true, "realized", &error_fatal);
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mmio), 0);
+ memory_region_add_subregion_overlap(&s->container, IOMEM_BASE, mr, -1500);
qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
qdev_init_nofail(DEVICE(&s->uart));
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index c9af9659e9..86bc304b57 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -13,8 +13,10 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/arm/armv7m.h"
+#include "hw/misc/unimp.h"
#include "hw/char/nrf51_uart.h"
+
#define TYPE_NRF51_SOC "nrf51-soc"
#define NRF51_SOC(obj) \
OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
@@ -27,12 +29,12 @@ typedef struct NRF51State {
/* TODO: Change to armv6m when cortex-m0 core is available */
ARMv7MState armv7m;
+ UnimplementedDeviceState mmio;
Nrf51UART uart;
MemoryRegion container;
MemoryRegion sram;
MemoryRegion flash;
- MemoryRegion iomem;
MemoryRegion clock;
MemoryRegion nvmc;
MemoryRegion rng;
--
2.17.1
next prev parent reply other threads:[~2018-06-27 7:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 7:33 [Qemu-devel] [RFC 0/8] arm: Changes to Microbit Board and NRF51 SOC Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 1/8] arm: NRF51/Microbit Memory container and SOC variants Steffen Görtz
2018-06-27 9:53 ` Stefan Hajnoczi
2018-06-27 7:33 ` Steffen Görtz [this message]
2018-06-27 7:33 ` [Qemu-devel] [RFC 3/8] arm: NRF51 create UART in-place, error handling Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 4/8] arm: NRF51 Calculate peripheral id from base address Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 5/8] arm: Add NRF51 random number generator peripheral Steffen Görtz
2018-07-05 16:51 ` Peter Maydell
2018-07-05 17:19 ` Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 6/8] arm: Add UICR/FICR handling to NRF51 SOC Steffen Görtz
2018-06-27 9:57 ` Stefan Hajnoczi
2018-06-27 7:33 ` [Qemu-devel] [RFC 7/8] arm: Add NRF51 SOC non-volatile memory controller Steffen Görtz
2018-06-27 7:33 ` [Qemu-devel] [RFC 8/8] arm: Instantiate NVMC in NRF51 Steffen Görtz
2018-06-27 9:46 ` [Qemu-devel] [RFC 0/8] arm: Changes to Microbit Board and NRF51 SOC Stefan Hajnoczi
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